Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.40 85.40 90.48 90.48 86.36 86.36 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/1.prim_esc_test.2197485463
89.03 3.63 93.33 2.86 86.36 0.00 100.00 0.00 89.29 14.29 83.72 4.65 81.48 0.00 /workspace/coverage/default/4.prim_esc_test.2608317927
90.17 1.14 94.29 0.95 86.36 0.00 100.00 0.00 92.86 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.1209481584
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.3627949462

Tests that do not contribute to grading

Name
/workspace/coverage/default/11.prim_esc_test.2695939396
/workspace/coverage/default/12.prim_esc_test.3294057997
/workspace/coverage/default/13.prim_esc_test.1270297719
/workspace/coverage/default/14.prim_esc_test.513118977
/workspace/coverage/default/15.prim_esc_test.2364556310
/workspace/coverage/default/16.prim_esc_test.1577176306
/workspace/coverage/default/17.prim_esc_test.3213184395
/workspace/coverage/default/18.prim_esc_test.3623647457
/workspace/coverage/default/19.prim_esc_test.528003371
/workspace/coverage/default/2.prim_esc_test.2403834972
/workspace/coverage/default/3.prim_esc_test.4215911693
/workspace/coverage/default/5.prim_esc_test.139620767
/workspace/coverage/default/6.prim_esc_test.2300216856
/workspace/coverage/default/7.prim_esc_test.2687105129
/workspace/coverage/default/8.prim_esc_test.1864585013
/workspace/coverage/default/9.prim_esc_test.3996539025



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_esc_test.3623647457 Mar 24 12:15:33 PM PDT 24 Mar 24 12:15:34 PM PDT 24 4105018 ps
T2 /workspace/coverage/default/1.prim_esc_test.2197485463 Mar 24 12:22:43 PM PDT 24 Mar 24 12:22:43 PM PDT 24 5328067 ps
T3 /workspace/coverage/default/7.prim_esc_test.2687105129 Mar 24 12:15:44 PM PDT 24 Mar 24 12:15:45 PM PDT 24 4829951 ps
T4 /workspace/coverage/default/15.prim_esc_test.2364556310 Mar 24 12:17:01 PM PDT 24 Mar 24 12:17:01 PM PDT 24 5013407 ps
T5 /workspace/coverage/default/12.prim_esc_test.3294057997 Mar 24 12:15:33 PM PDT 24 Mar 24 12:15:34 PM PDT 24 5018777 ps
T11 /workspace/coverage/default/9.prim_esc_test.3996539025 Mar 24 12:22:21 PM PDT 24 Mar 24 12:22:22 PM PDT 24 5019474 ps
T13 /workspace/coverage/default/17.prim_esc_test.3213184395 Mar 24 12:22:39 PM PDT 24 Mar 24 12:22:40 PM PDT 24 4938085 ps
T14 /workspace/coverage/default/16.prim_esc_test.1577176306 Mar 24 12:18:04 PM PDT 24 Mar 24 12:18:05 PM PDT 24 4589391 ps
T15 /workspace/coverage/default/19.prim_esc_test.528003371 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 4505576 ps
T16 /workspace/coverage/default/10.prim_esc_test.3627949462 Mar 24 12:22:00 PM PDT 24 Mar 24 12:22:01 PM PDT 24 5637915 ps
T6 /workspace/coverage/default/0.prim_esc_test.1209481584 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:10 PM PDT 24 4890290 ps
T17 /workspace/coverage/default/14.prim_esc_test.513118977 Mar 24 12:23:06 PM PDT 24 Mar 24 12:23:07 PM PDT 24 4939469 ps
T12 /workspace/coverage/default/5.prim_esc_test.139620767 Mar 24 12:19:43 PM PDT 24 Mar 24 12:19:44 PM PDT 24 4832925 ps
T8 /workspace/coverage/default/4.prim_esc_test.2608317927 Mar 24 12:15:57 PM PDT 24 Mar 24 12:15:57 PM PDT 24 4790244 ps
T18 /workspace/coverage/default/8.prim_esc_test.1864585013 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:10 PM PDT 24 5191428 ps
T9 /workspace/coverage/default/6.prim_esc_test.2300216856 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:55 PM PDT 24 5210461 ps
T10 /workspace/coverage/default/3.prim_esc_test.4215911693 Mar 24 12:20:02 PM PDT 24 Mar 24 12:20:03 PM PDT 24 5041455 ps
T7 /workspace/coverage/default/2.prim_esc_test.2403834972 Mar 24 12:15:27 PM PDT 24 Mar 24 12:15:28 PM PDT 24 4391242 ps
T19 /workspace/coverage/default/13.prim_esc_test.1270297719 Mar 24 12:18:04 PM PDT 24 Mar 24 12:18:05 PM PDT 24 5055578 ps
T20 /workspace/coverage/default/11.prim_esc_test.2695939396 Mar 24 12:17:47 PM PDT 24 Mar 24 12:17:48 PM PDT 24 4891415 ps

Test location /workspace/coverage/default/1.prim_esc_test.2197485463
Short name T2
Test name
Test status
Simulation time 5328067 ps
CPU time 0.36 seconds
Started Mar 24 12:22:43 PM PDT 24
Finished Mar 24 12:22:43 PM PDT 24
Peak memory 146300 kb
Host smart-9a81ea79-ef79-4de5-9441-a90402ae7ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197485463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2197485463
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2608317927
Short name T8
Test name
Test status
Simulation time 4790244 ps
CPU time 0.4 seconds
Started Mar 24 12:15:57 PM PDT 24
Finished Mar 24 12:15:57 PM PDT 24
Peak memory 146308 kb
Host smart-2b1d32fb-531f-41fc-b0cd-a03ccb7f41d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608317927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2608317927
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.1209481584
Short name T6
Test name
Test status
Simulation time 4890290 ps
CPU time 0.41 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 146100 kb
Host smart-32274b63-4d61-4e3b-b12c-af5c6fbf8a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209481584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1209481584
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3627949462
Short name T16
Test name
Test status
Simulation time 5637915 ps
CPU time 0.38 seconds
Started Mar 24 12:22:00 PM PDT 24
Finished Mar 24 12:22:01 PM PDT 24
Peak memory 145824 kb
Host smart-3b8e6955-3215-4feb-b1f9-c58cd15d6c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627949462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3627949462
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2695939396
Short name T20
Test name
Test status
Simulation time 4891415 ps
CPU time 0.4 seconds
Started Mar 24 12:17:47 PM PDT 24
Finished Mar 24 12:17:48 PM PDT 24
Peak memory 145648 kb
Host smart-a6bc2e36-0745-454e-92df-ba4fd3fe2805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695939396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2695939396
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.3294057997
Short name T5
Test name
Test status
Simulation time 5018777 ps
CPU time 0.4 seconds
Started Mar 24 12:15:33 PM PDT 24
Finished Mar 24 12:15:34 PM PDT 24
Peak memory 146588 kb
Host smart-a95ec8fd-b5ef-4d40-a441-8739796d357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294057997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3294057997
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1270297719
Short name T19
Test name
Test status
Simulation time 5055578 ps
CPU time 0.4 seconds
Started Mar 24 12:18:04 PM PDT 24
Finished Mar 24 12:18:05 PM PDT 24
Peak memory 145968 kb
Host smart-9618c1d9-a6c3-4f6a-8439-4ae0627da8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270297719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1270297719
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.513118977
Short name T17
Test name
Test status
Simulation time 4939469 ps
CPU time 0.42 seconds
Started Mar 24 12:23:06 PM PDT 24
Finished Mar 24 12:23:07 PM PDT 24
Peak memory 146248 kb
Host smart-ca3cf461-3980-4d6f-a9eb-e95b87c1a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513118977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.513118977
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2364556310
Short name T4
Test name
Test status
Simulation time 5013407 ps
CPU time 0.4 seconds
Started Mar 24 12:17:01 PM PDT 24
Finished Mar 24 12:17:01 PM PDT 24
Peak memory 146424 kb
Host smart-32ebc2f4-2186-4dbc-99ea-bfd35b0f95cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364556310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2364556310
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1577176306
Short name T14
Test name
Test status
Simulation time 4589391 ps
CPU time 0.39 seconds
Started Mar 24 12:18:04 PM PDT 24
Finished Mar 24 12:18:05 PM PDT 24
Peak memory 145968 kb
Host smart-0e257191-3118-45c1-9978-a505d72da9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577176306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1577176306
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3213184395
Short name T13
Test name
Test status
Simulation time 4938085 ps
CPU time 0.39 seconds
Started Mar 24 12:22:39 PM PDT 24
Finished Mar 24 12:22:40 PM PDT 24
Peak memory 145936 kb
Host smart-8b30d2e2-f4a0-4e30-970d-f5f6a6d94344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213184395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3213184395
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3623647457
Short name T1
Test name
Test status
Simulation time 4105018 ps
CPU time 0.43 seconds
Started Mar 24 12:15:33 PM PDT 24
Finished Mar 24 12:15:34 PM PDT 24
Peak memory 146588 kb
Host smart-4c032fd7-3047-4567-ac98-bb7f5aad2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623647457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3623647457
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.528003371
Short name T15
Test name
Test status
Simulation time 4505576 ps
CPU time 0.38 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 146252 kb
Host smart-da985e61-679f-46bf-83fd-6611c4704ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528003371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.528003371
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2403834972
Short name T7
Test name
Test status
Simulation time 4391242 ps
CPU time 0.38 seconds
Started Mar 24 12:15:27 PM PDT 24
Finished Mar 24 12:15:28 PM PDT 24
Peak memory 146408 kb
Host smart-381644e1-9891-4d6f-8aeb-9f82ef42773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403834972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2403834972
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.4215911693
Short name T10
Test name
Test status
Simulation time 5041455 ps
CPU time 0.4 seconds
Started Mar 24 12:20:02 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 145536 kb
Host smart-8263efcd-3215-4efb-9447-e5c5e10a8532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215911693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4215911693
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.139620767
Short name T12
Test name
Test status
Simulation time 4832925 ps
CPU time 0.39 seconds
Started Mar 24 12:19:43 PM PDT 24
Finished Mar 24 12:19:44 PM PDT 24
Peak memory 146352 kb
Host smart-e889c714-938e-432e-a82e-fe4197205c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139620767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.139620767
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2300216856
Short name T9
Test name
Test status
Simulation time 5210461 ps
CPU time 0.38 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:55 PM PDT 24
Peak memory 146252 kb
Host smart-564db4de-619c-46ce-9b51-cfb2f28038a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300216856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2300216856
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.2687105129
Short name T3
Test name
Test status
Simulation time 4829951 ps
CPU time 0.39 seconds
Started Mar 24 12:15:44 PM PDT 24
Finished Mar 24 12:15:45 PM PDT 24
Peak memory 146588 kb
Host smart-92f86542-830b-40e6-b8fd-c18111fe7b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687105129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2687105129
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.1864585013
Short name T18
Test name
Test status
Simulation time 5191428 ps
CPU time 0.41 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 146004 kb
Host smart-0a285797-5f48-42b2-bef8-715e7bcee59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864585013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1864585013
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3996539025
Short name T11
Test name
Test status
Simulation time 5019474 ps
CPU time 0.41 seconds
Started Mar 24 12:22:21 PM PDT 24
Finished Mar 24 12:22:22 PM PDT 24
Peak memory 146272 kb
Host smart-6b0ec8ad-7c25-415e-a952-33feedc84654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996539025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3996539025
Directory /workspace/9.prim_esc_test/latest
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