Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.40 85.40 90.48 90.48 86.36 86.36 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/4.prim_esc_test.160523020
88.44 3.04 93.33 2.86 86.36 0.00 100.00 0.00 85.71 10.71 83.72 4.65 81.48 0.00 /workspace/coverage/default/2.prim_esc_test.2205653681
90.17 1.74 94.29 0.95 86.36 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.1541123183
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.3559137006

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.4273987077
/workspace/coverage/default/1.prim_esc_test.2890151211
/workspace/coverage/default/10.prim_esc_test.1877292543
/workspace/coverage/default/11.prim_esc_test.1185796265
/workspace/coverage/default/12.prim_esc_test.2225595109
/workspace/coverage/default/13.prim_esc_test.1298130683
/workspace/coverage/default/14.prim_esc_test.332010643
/workspace/coverage/default/16.prim_esc_test.1435120209
/workspace/coverage/default/17.prim_esc_test.1176942345
/workspace/coverage/default/18.prim_esc_test.3796806496
/workspace/coverage/default/3.prim_esc_test.2120704151
/workspace/coverage/default/5.prim_esc_test.832199769
/workspace/coverage/default/6.prim_esc_test.127155948
/workspace/coverage/default/7.prim_esc_test.3795978511
/workspace/coverage/default/8.prim_esc_test.95325098
/workspace/coverage/default/9.prim_esc_test.2735250599



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.prim_esc_test.2890151211 Mar 26 12:31:53 PM PDT 24 Mar 26 12:31:54 PM PDT 24 4788585 ps
T2 /workspace/coverage/default/10.prim_esc_test.1877292543 Mar 26 12:31:57 PM PDT 24 Mar 26 12:31:58 PM PDT 24 5037474 ps
T3 /workspace/coverage/default/12.prim_esc_test.2225595109 Mar 26 12:31:54 PM PDT 24 Mar 26 12:31:54 PM PDT 24 4883757 ps
T4 /workspace/coverage/default/0.prim_esc_test.4273987077 Mar 26 12:31:51 PM PDT 24 Mar 26 12:31:52 PM PDT 24 4596533 ps
T8 /workspace/coverage/default/18.prim_esc_test.3796806496 Mar 26 12:32:07 PM PDT 24 Mar 26 12:32:08 PM PDT 24 5056520 ps
T10 /workspace/coverage/default/4.prim_esc_test.160523020 Mar 26 12:31:53 PM PDT 24 Mar 26 12:31:54 PM PDT 24 4922646 ps
T13 /workspace/coverage/default/5.prim_esc_test.832199769 Mar 26 12:31:56 PM PDT 24 Mar 26 12:31:56 PM PDT 24 4305026 ps
T11 /workspace/coverage/default/7.prim_esc_test.3795978511 Mar 26 12:31:53 PM PDT 24 Mar 26 12:31:54 PM PDT 24 4899883 ps
T5 /workspace/coverage/default/9.prim_esc_test.2735250599 Mar 26 12:31:59 PM PDT 24 Mar 26 12:32:00 PM PDT 24 4287807 ps
T14 /workspace/coverage/default/14.prim_esc_test.332010643 Mar 26 12:32:05 PM PDT 24 Mar 26 12:32:05 PM PDT 24 4423790 ps
T6 /workspace/coverage/default/3.prim_esc_test.2120704151 Mar 26 12:31:55 PM PDT 24 Mar 26 12:31:56 PM PDT 24 5103146 ps
T16 /workspace/coverage/default/8.prim_esc_test.95325098 Mar 26 12:31:55 PM PDT 24 Mar 26 12:31:56 PM PDT 24 4600541 ps
T15 /workspace/coverage/default/19.prim_esc_test.1541123183 Mar 26 12:32:03 PM PDT 24 Mar 26 12:32:04 PM PDT 24 4945208 ps
T12 /workspace/coverage/default/11.prim_esc_test.1185796265 Mar 26 12:31:54 PM PDT 24 Mar 26 12:31:54 PM PDT 24 4415457 ps
T9 /workspace/coverage/default/2.prim_esc_test.2205653681 Mar 26 12:31:53 PM PDT 24 Mar 26 12:31:53 PM PDT 24 4863493 ps
T17 /workspace/coverage/default/6.prim_esc_test.127155948 Mar 26 12:31:55 PM PDT 24 Mar 26 12:31:56 PM PDT 24 4958984 ps
T7 /workspace/coverage/default/15.prim_esc_test.3559137006 Mar 26 12:32:06 PM PDT 24 Mar 26 12:32:06 PM PDT 24 4234427 ps
T18 /workspace/coverage/default/13.prim_esc_test.1298130683 Mar 26 12:32:01 PM PDT 24 Mar 26 12:32:01 PM PDT 24 4909354 ps
T19 /workspace/coverage/default/16.prim_esc_test.1435120209 Mar 26 12:32:08 PM PDT 24 Mar 26 12:32:08 PM PDT 24 4625796 ps
T20 /workspace/coverage/default/17.prim_esc_test.1176942345 Mar 26 12:32:02 PM PDT 24 Mar 26 12:32:03 PM PDT 24 4967429 ps

Test location /workspace/coverage/default/4.prim_esc_test.160523020
Short name T10
Test name
Test status
Simulation time 4922646 ps
CPU time 0.38 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 146336 kb
Host smart-dee89083-215a-497a-9dba-ba233e241c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160523020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.160523020
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2205653681
Short name T9
Test name
Test status
Simulation time 4863493 ps
CPU time 0.37 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 146312 kb
Host smart-a33bd751-cfe0-45bd-8d73-1ca6e68f9bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205653681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2205653681
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1541123183
Short name T15
Test name
Test status
Simulation time 4945208 ps
CPU time 0.41 seconds
Started Mar 26 12:32:03 PM PDT 24
Finished Mar 26 12:32:04 PM PDT 24
Peak memory 146352 kb
Host smart-5eba2cbd-a1bc-4068-9daa-03742153ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541123183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1541123183
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3559137006
Short name T7
Test name
Test status
Simulation time 4234427 ps
CPU time 0.36 seconds
Started Mar 26 12:32:06 PM PDT 24
Finished Mar 26 12:32:06 PM PDT 24
Peak memory 146344 kb
Host smart-9122b546-525b-47fe-922e-0c4ebd4206b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559137006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3559137006
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.4273987077
Short name T4
Test name
Test status
Simulation time 4596533 ps
CPU time 0.37 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 146320 kb
Host smart-91a6e812-f564-4085-83df-d27af73a3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273987077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4273987077
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.2890151211
Short name T1
Test name
Test status
Simulation time 4788585 ps
CPU time 0.37 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 146352 kb
Host smart-24bbaaa5-b8f3-447c-ac2d-4fb9bec774e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890151211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2890151211
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1877292543
Short name T2
Test name
Test status
Simulation time 5037474 ps
CPU time 0.36 seconds
Started Mar 26 12:31:57 PM PDT 24
Finished Mar 26 12:31:58 PM PDT 24
Peak memory 146324 kb
Host smart-07b847f7-4bab-487e-a403-42589d127905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877292543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1877292543
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1185796265
Short name T12
Test name
Test status
Simulation time 4415457 ps
CPU time 0.41 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 146344 kb
Host smart-6fdd13ee-522c-4636-97a1-8e38161dd330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185796265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1185796265
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.2225595109
Short name T3
Test name
Test status
Simulation time 4883757 ps
CPU time 0.36 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 146324 kb
Host smart-539f1703-b5b7-4207-9c19-aa67fa276865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225595109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2225595109
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1298130683
Short name T18
Test name
Test status
Simulation time 4909354 ps
CPU time 0.37 seconds
Started Mar 26 12:32:01 PM PDT 24
Finished Mar 26 12:32:01 PM PDT 24
Peak memory 146344 kb
Host smart-92f10a91-cfff-45cf-b119-e3bc7fc6687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298130683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1298130683
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.332010643
Short name T14
Test name
Test status
Simulation time 4423790 ps
CPU time 0.35 seconds
Started Mar 26 12:32:05 PM PDT 24
Finished Mar 26 12:32:05 PM PDT 24
Peak memory 146316 kb
Host smart-862490fd-5252-4324-8dfd-06ff6198974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332010643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.332010643
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1435120209
Short name T19
Test name
Test status
Simulation time 4625796 ps
CPU time 0.37 seconds
Started Mar 26 12:32:08 PM PDT 24
Finished Mar 26 12:32:08 PM PDT 24
Peak memory 146280 kb
Host smart-716caeb1-46ff-4085-a5d6-10636dce233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435120209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1435120209
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1176942345
Short name T20
Test name
Test status
Simulation time 4967429 ps
CPU time 0.4 seconds
Started Mar 26 12:32:02 PM PDT 24
Finished Mar 26 12:32:03 PM PDT 24
Peak memory 146320 kb
Host smart-5581a8c2-f9d1-4847-9366-4dd5e07fda17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176942345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1176942345
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3796806496
Short name T8
Test name
Test status
Simulation time 5056520 ps
CPU time 0.38 seconds
Started Mar 26 12:32:07 PM PDT 24
Finished Mar 26 12:32:08 PM PDT 24
Peak memory 146352 kb
Host smart-a30cdb21-97d8-489b-950a-cecae9f987a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796806496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3796806496
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2120704151
Short name T6
Test name
Test status
Simulation time 5103146 ps
CPU time 0.36 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 146328 kb
Host smart-fbb7cbc0-eb4d-4d09-852d-0447e0c15537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120704151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2120704151
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.832199769
Short name T13
Test name
Test status
Simulation time 4305026 ps
CPU time 0.38 seconds
Started Mar 26 12:31:56 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 146332 kb
Host smart-561012d2-2d96-4937-bf36-ff94a783d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832199769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.832199769
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.127155948
Short name T17
Test name
Test status
Simulation time 4958984 ps
CPU time 0.37 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 146360 kb
Host smart-e5a419a6-c5b2-4046-acfc-1f476f8f99bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127155948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.127155948
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3795978511
Short name T11
Test name
Test status
Simulation time 4899883 ps
CPU time 0.39 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 146328 kb
Host smart-962b91ba-5272-4e50-af38-824138744afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795978511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3795978511
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.95325098
Short name T16
Test name
Test status
Simulation time 4600541 ps
CPU time 0.38 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 146416 kb
Host smart-e220df2f-5335-47c0-932f-2378e7168822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95325098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.95325098
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2735250599
Short name T5
Test name
Test status
Simulation time 4287807 ps
CPU time 0.36 seconds
Started Mar 26 12:31:59 PM PDT 24
Finished Mar 26 12:32:00 PM PDT 24
Peak memory 146272 kb
Host smart-4a9ca82e-ff63-4a58-80ed-ac6b8b6a7373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735250599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2735250599
Directory /workspace/9.prim_esc_test/latest
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