Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.70 86.70 92.38 92.38 86.36 86.36 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/4.prim_esc_test.2868865566
88.44 1.74 93.33 0.95 86.36 0.00 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.323142211
89.58 1.14 94.29 0.95 86.36 0.00 100.00 0.00 89.29 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.3040786070
90.72 1.14 95.24 0.95 86.36 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/18.prim_esc_test.492235764
91.31 0.60 95.24 0.00 86.36 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.874579249

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.704466772
/workspace/coverage/default/11.prim_esc_test.2565002698
/workspace/coverage/default/12.prim_esc_test.2576473894
/workspace/coverage/default/13.prim_esc_test.976417514
/workspace/coverage/default/14.prim_esc_test.2965851901
/workspace/coverage/default/16.prim_esc_test.3202402732
/workspace/coverage/default/17.prim_esc_test.4284580360
/workspace/coverage/default/19.prim_esc_test.963128228
/workspace/coverage/default/2.prim_esc_test.725424841
/workspace/coverage/default/3.prim_esc_test.2379726326
/workspace/coverage/default/5.prim_esc_test.4008076216
/workspace/coverage/default/6.prim_esc_test.594499154
/workspace/coverage/default/7.prim_esc_test.1896925743
/workspace/coverage/default/8.prim_esc_test.3963828555
/workspace/coverage/default/9.prim_esc_test.2716516088



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_esc_test.492235764 Mar 28 12:21:03 PM PDT 24 Mar 28 12:21:04 PM PDT 24 4687020 ps
T2 /workspace/coverage/default/15.prim_esc_test.323142211 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:47 PM PDT 24 4896532 ps
T3 /workspace/coverage/default/10.prim_esc_test.874579249 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:48 PM PDT 24 5288550 ps
T4 /workspace/coverage/default/4.prim_esc_test.2868865566 Mar 28 12:16:28 PM PDT 24 Mar 28 12:16:29 PM PDT 24 4631872 ps
T7 /workspace/coverage/default/7.prim_esc_test.1896925743 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:46 PM PDT 24 5271619 ps
T8 /workspace/coverage/default/19.prim_esc_test.963128228 Mar 28 12:18:35 PM PDT 24 Mar 28 12:18:35 PM PDT 24 4281992 ps
T10 /workspace/coverage/default/5.prim_esc_test.4008076216 Mar 28 12:16:48 PM PDT 24 Mar 28 12:16:48 PM PDT 24 4514785 ps
T11 /workspace/coverage/default/2.prim_esc_test.725424841 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 4811031 ps
T12 /workspace/coverage/default/16.prim_esc_test.3202402732 Mar 28 12:17:03 PM PDT 24 Mar 28 12:17:04 PM PDT 24 5126660 ps
T5 /workspace/coverage/default/0.prim_esc_test.3040786070 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 4965589 ps
T6 /workspace/coverage/default/14.prim_esc_test.2965851901 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:47 PM PDT 24 4299519 ps
T15 /workspace/coverage/default/3.prim_esc_test.2379726326 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:46 PM PDT 24 5196396 ps
T16 /workspace/coverage/default/12.prim_esc_test.2576473894 Mar 28 12:16:41 PM PDT 24 Mar 28 12:16:48 PM PDT 24 4688625 ps
T17 /workspace/coverage/default/8.prim_esc_test.3963828555 Mar 28 12:19:33 PM PDT 24 Mar 28 12:19:34 PM PDT 24 5252925 ps
T13 /workspace/coverage/default/17.prim_esc_test.4284580360 Mar 28 12:16:36 PM PDT 24 Mar 28 12:16:37 PM PDT 24 4312282 ps
T18 /workspace/coverage/default/11.prim_esc_test.2565002698 Mar 28 12:23:18 PM PDT 24 Mar 28 12:23:19 PM PDT 24 4939171 ps
T9 /workspace/coverage/default/13.prim_esc_test.976417514 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:46 PM PDT 24 4780362 ps
T14 /workspace/coverage/default/6.prim_esc_test.594499154 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:48 PM PDT 24 5124463 ps
T19 /workspace/coverage/default/1.prim_esc_test.704466772 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 5150919 ps
T20 /workspace/coverage/default/9.prim_esc_test.2716516088 Mar 28 12:16:41 PM PDT 24 Mar 28 12:16:48 PM PDT 24 4761631 ps

Test location /workspace/coverage/default/4.prim_esc_test.2868865566
Short name T4
Test name
Test status
Simulation time 4631872 ps
CPU time 0.38 seconds
Started Mar 28 12:16:28 PM PDT 24
Finished Mar 28 12:16:29 PM PDT 24
Peak memory 146552 kb
Host smart-2637169e-4e26-431f-b7c0-c0ae7665bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868865566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2868865566
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.323142211
Short name T2
Test name
Test status
Simulation time 4896532 ps
CPU time 0.37 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 146192 kb
Host smart-18ecdade-282c-45b2-a47d-d155bc1aeef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323142211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.323142211
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3040786070
Short name T5
Test name
Test status
Simulation time 4965589 ps
CPU time 0.39 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146412 kb
Host smart-f2b42165-e62c-49b5-ae64-424c1663428d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040786070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3040786070
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.492235764
Short name T1
Test name
Test status
Simulation time 4687020 ps
CPU time 0.38 seconds
Started Mar 28 12:21:03 PM PDT 24
Finished Mar 28 12:21:04 PM PDT 24
Peak memory 146568 kb
Host smart-248223be-8d31-4f3c-9691-471609b7c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492235764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.492235764
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.874579249
Short name T3
Test name
Test status
Simulation time 5288550 ps
CPU time 0.4 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146436 kb
Host smart-71d5006b-4526-414c-b2e3-18449457a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874579249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.874579249
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.704466772
Short name T19
Test name
Test status
Simulation time 5150919 ps
CPU time 0.42 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146396 kb
Host smart-09d63a53-0a2d-4acc-80b6-b27dc2068ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704466772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.704466772
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2565002698
Short name T18
Test name
Test status
Simulation time 4939171 ps
CPU time 0.45 seconds
Started Mar 28 12:23:18 PM PDT 24
Finished Mar 28 12:23:19 PM PDT 24
Peak memory 145992 kb
Host smart-cc300b34-1342-429d-8885-898279b62266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565002698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2565002698
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.2576473894
Short name T16
Test name
Test status
Simulation time 4688625 ps
CPU time 0.43 seconds
Started Mar 28 12:16:41 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146404 kb
Host smart-26c7ce2f-469c-4c0c-979e-0be956878dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576473894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2576473894
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.976417514
Short name T9
Test name
Test status
Simulation time 4780362 ps
CPU time 0.37 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:46 PM PDT 24
Peak memory 146412 kb
Host smart-83dfe196-a537-4660-a596-8bd78c7b829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976417514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.976417514
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2965851901
Short name T6
Test name
Test status
Simulation time 4299519 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 146124 kb
Host smart-8522bdb7-4d5f-4bd1-ba50-114f873672e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965851901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2965851901
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.3202402732
Short name T12
Test name
Test status
Simulation time 5126660 ps
CPU time 0.37 seconds
Started Mar 28 12:17:03 PM PDT 24
Finished Mar 28 12:17:04 PM PDT 24
Peak memory 146020 kb
Host smart-c867ffc4-32ae-44f7-b3cb-e49606024d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202402732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3202402732
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.4284580360
Short name T13
Test name
Test status
Simulation time 4312282 ps
CPU time 0.4 seconds
Started Mar 28 12:16:36 PM PDT 24
Finished Mar 28 12:16:37 PM PDT 24
Peak memory 145948 kb
Host smart-bf1ddd6a-1551-4886-b0c7-b61f27210a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284580360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.4284580360
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.963128228
Short name T8
Test name
Test status
Simulation time 4281992 ps
CPU time 0.39 seconds
Started Mar 28 12:18:35 PM PDT 24
Finished Mar 28 12:18:35 PM PDT 24
Peak memory 146420 kb
Host smart-3211ddb8-829c-41aa-be5c-c17f047d1d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963128228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.963128228
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.725424841
Short name T11
Test name
Test status
Simulation time 4811031 ps
CPU time 0.37 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146396 kb
Host smart-9bd161c9-915b-4759-aa4a-1c0729b514f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725424841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.725424841
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2379726326
Short name T15
Test name
Test status
Simulation time 5196396 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:46 PM PDT 24
Peak memory 146424 kb
Host smart-f57b7876-9926-4241-93b5-fd366f2fbe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379726326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2379726326
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.4008076216
Short name T10
Test name
Test status
Simulation time 4514785 ps
CPU time 0.39 seconds
Started Mar 28 12:16:48 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146016 kb
Host smart-5bdea3b4-6332-486c-a7f8-8eec4c7a35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008076216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4008076216
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.594499154
Short name T14
Test name
Test status
Simulation time 5124463 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146436 kb
Host smart-ac31e58d-6ad0-4439-8b9e-d8f238192206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594499154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.594499154
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.1896925743
Short name T7
Test name
Test status
Simulation time 5271619 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:46 PM PDT 24
Peak memory 146424 kb
Host smart-b39e19fd-090f-4c4c-8d97-73d7dbd80bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896925743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1896925743
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3963828555
Short name T17
Test name
Test status
Simulation time 5252925 ps
CPU time 0.47 seconds
Started Mar 28 12:19:33 PM PDT 24
Finished Mar 28 12:19:34 PM PDT 24
Peak memory 146264 kb
Host smart-bb9e4b2e-2d76-4abc-adaa-1206dee8ddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963828555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3963828555
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2716516088
Short name T20
Test name
Test status
Simulation time 4761631 ps
CPU time 0.37 seconds
Started Mar 28 12:16:41 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 146412 kb
Host smart-6582a5bc-221f-4936-a9ac-d9c932462a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716516088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2716516088
Directory /workspace/9.prim_esc_test/latest
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