Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.80 84.80 90.48 90.48 86.36 86.36 100.00 100.00 71.43 71.43 79.07 79.07 81.48 81.48 /workspace/coverage/default/8.prim_esc_test.765853039
88.44 3.63 93.33 2.86 86.36 0.00 100.00 0.00 85.71 14.29 83.72 4.65 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.2373185838
90.17 1.74 94.29 0.95 86.36 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/17.prim_esc_test.1098124235
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.1743696321

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.2143452216
/workspace/coverage/default/10.prim_esc_test.2168170851
/workspace/coverage/default/11.prim_esc_test.1127155198
/workspace/coverage/default/12.prim_esc_test.3958370671
/workspace/coverage/default/13.prim_esc_test.3910849028
/workspace/coverage/default/14.prim_esc_test.3958687692
/workspace/coverage/default/16.prim_esc_test.3883921936
/workspace/coverage/default/18.prim_esc_test.3731340362
/workspace/coverage/default/19.prim_esc_test.671811552
/workspace/coverage/default/2.prim_esc_test.3139034925
/workspace/coverage/default/3.prim_esc_test.3105281779
/workspace/coverage/default/4.prim_esc_test.2493131550
/workspace/coverage/default/5.prim_esc_test.1830707938
/workspace/coverage/default/6.prim_esc_test.4193620158
/workspace/coverage/default/7.prim_esc_test.257867349
/workspace/coverage/default/9.prim_esc_test.3370111358



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/17.prim_esc_test.1098124235 Mar 31 12:35:57 PM PDT 24 Mar 31 12:35:58 PM PDT 24 4848139 ps
T2 /workspace/coverage/default/8.prim_esc_test.765853039 Mar 31 12:35:59 PM PDT 24 Mar 31 12:36:00 PM PDT 24 5180481 ps
T3 /workspace/coverage/default/5.prim_esc_test.1830707938 Mar 31 12:36:06 PM PDT 24 Mar 31 12:36:06 PM PDT 24 4669412 ps
T5 /workspace/coverage/default/3.prim_esc_test.3105281779 Mar 31 12:35:55 PM PDT 24 Mar 31 12:35:56 PM PDT 24 5092825 ps
T8 /workspace/coverage/default/0.prim_esc_test.1743696321 Mar 31 12:36:00 PM PDT 24 Mar 31 12:36:00 PM PDT 24 4817979 ps
T14 /workspace/coverage/default/2.prim_esc_test.3139034925 Mar 31 12:35:57 PM PDT 24 Mar 31 12:35:58 PM PDT 24 4961781 ps
T9 /workspace/coverage/default/16.prim_esc_test.3883921936 Mar 31 12:35:59 PM PDT 24 Mar 31 12:36:00 PM PDT 24 5169394 ps
T15 /workspace/coverage/default/11.prim_esc_test.1127155198 Mar 31 12:36:12 PM PDT 24 Mar 31 12:36:13 PM PDT 24 4760834 ps
T4 /workspace/coverage/default/1.prim_esc_test.2143452216 Mar 31 12:36:12 PM PDT 24 Mar 31 12:36:13 PM PDT 24 4675715 ps
T16 /workspace/coverage/default/18.prim_esc_test.3731340362 Mar 31 12:36:15 PM PDT 24 Mar 31 12:36:16 PM PDT 24 4692204 ps
T11 /workspace/coverage/default/7.prim_esc_test.257867349 Mar 31 12:35:55 PM PDT 24 Mar 31 12:35:56 PM PDT 24 4117497 ps
T12 /workspace/coverage/default/6.prim_esc_test.4193620158 Mar 31 12:36:04 PM PDT 24 Mar 31 12:36:05 PM PDT 24 4910459 ps
T10 /workspace/coverage/default/13.prim_esc_test.3910849028 Mar 31 12:35:54 PM PDT 24 Mar 31 12:35:55 PM PDT 24 5297802 ps
T6 /workspace/coverage/default/15.prim_esc_test.2373185838 Mar 31 12:35:58 PM PDT 24 Mar 31 12:35:58 PM PDT 24 4557146 ps
T17 /workspace/coverage/default/14.prim_esc_test.3958687692 Mar 31 12:36:21 PM PDT 24 Mar 31 12:36:22 PM PDT 24 4881216 ps
T7 /workspace/coverage/default/4.prim_esc_test.2493131550 Mar 31 12:35:59 PM PDT 24 Mar 31 12:35:59 PM PDT 24 4249901 ps
T13 /workspace/coverage/default/19.prim_esc_test.671811552 Mar 31 12:35:54 PM PDT 24 Mar 31 12:35:54 PM PDT 24 5388373 ps
T18 /workspace/coverage/default/10.prim_esc_test.2168170851 Mar 31 12:36:08 PM PDT 24 Mar 31 12:36:09 PM PDT 24 4165354 ps
T19 /workspace/coverage/default/12.prim_esc_test.3958370671 Mar 31 12:35:58 PM PDT 24 Mar 31 12:35:59 PM PDT 24 5025426 ps
T20 /workspace/coverage/default/9.prim_esc_test.3370111358 Mar 31 12:35:55 PM PDT 24 Mar 31 12:35:56 PM PDT 24 4929698 ps

Test location /workspace/coverage/default/8.prim_esc_test.765853039
Short name T2
Test name
Test status
Simulation time 5180481 ps
CPU time 0.37 seconds
Started Mar 31 12:35:59 PM PDT 24
Finished Mar 31 12:36:00 PM PDT 24
Peak memory 146460 kb
Host smart-37e2198f-eab2-46b1-b352-1b399bfeb59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765853039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.765853039
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2373185838
Short name T6
Test name
Test status
Simulation time 4557146 ps
CPU time 0.37 seconds
Started Mar 31 12:35:58 PM PDT 24
Finished Mar 31 12:35:58 PM PDT 24
Peak memory 146372 kb
Host smart-83b9a50f-7fad-48e8-8590-1643293cef48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373185838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2373185838
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1098124235
Short name T1
Test name
Test status
Simulation time 4848139 ps
CPU time 0.37 seconds
Started Mar 31 12:35:57 PM PDT 24
Finished Mar 31 12:35:58 PM PDT 24
Peak memory 146364 kb
Host smart-55d488a1-dc7d-47de-96a1-c89e429fa67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098124235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1098124235
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.1743696321
Short name T8
Test name
Test status
Simulation time 4817979 ps
CPU time 0.37 seconds
Started Mar 31 12:36:00 PM PDT 24
Finished Mar 31 12:36:00 PM PDT 24
Peak memory 146392 kb
Host smart-ea6cbda7-1a53-446c-8c7c-518b16aac3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743696321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1743696321
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.2143452216
Short name T4
Test name
Test status
Simulation time 4675715 ps
CPU time 0.38 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 146372 kb
Host smart-7d6ef850-a403-4cb9-b843-bbca8d92db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143452216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2143452216
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2168170851
Short name T18
Test name
Test status
Simulation time 4165354 ps
CPU time 0.38 seconds
Started Mar 31 12:36:08 PM PDT 24
Finished Mar 31 12:36:09 PM PDT 24
Peak memory 146396 kb
Host smart-a7353c7a-7763-4db7-8fee-5910b2299458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168170851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2168170851
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1127155198
Short name T15
Test name
Test status
Simulation time 4760834 ps
CPU time 0.38 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 146372 kb
Host smart-9626ddc9-67ff-47cb-bc9b-bd1200c18982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127155198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1127155198
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.3958370671
Short name T19
Test name
Test status
Simulation time 5025426 ps
CPU time 0.37 seconds
Started Mar 31 12:35:58 PM PDT 24
Finished Mar 31 12:35:59 PM PDT 24
Peak memory 146364 kb
Host smart-cd294b01-500f-4d6f-b283-3745ba44e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958370671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3958370671
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.3910849028
Short name T10
Test name
Test status
Simulation time 5297802 ps
CPU time 0.37 seconds
Started Mar 31 12:35:54 PM PDT 24
Finished Mar 31 12:35:55 PM PDT 24
Peak memory 146484 kb
Host smart-6b754c95-00ed-4a26-85c6-0e7441d9a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910849028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3910849028
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3958687692
Short name T17
Test name
Test status
Simulation time 4881216 ps
CPU time 0.38 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 146484 kb
Host smart-246a25c8-f0c4-4010-a4f1-d533498c4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958687692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3958687692
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.3883921936
Short name T9
Test name
Test status
Simulation time 5169394 ps
CPU time 0.37 seconds
Started Mar 31 12:35:59 PM PDT 24
Finished Mar 31 12:36:00 PM PDT 24
Peak memory 146432 kb
Host smart-3a345705-0ab7-4656-ad06-6235d84b68e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883921936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3883921936
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3731340362
Short name T16
Test name
Test status
Simulation time 4692204 ps
CPU time 0.38 seconds
Started Mar 31 12:36:15 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 146448 kb
Host smart-315c99c5-2e57-42fb-9ded-aad28e20db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731340362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3731340362
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.671811552
Short name T13
Test name
Test status
Simulation time 5388373 ps
CPU time 0.36 seconds
Started Mar 31 12:35:54 PM PDT 24
Finished Mar 31 12:35:54 PM PDT 24
Peak memory 146476 kb
Host smart-d2c2664a-b33e-479f-9b82-23fa034fbeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671811552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.671811552
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3139034925
Short name T14
Test name
Test status
Simulation time 4961781 ps
CPU time 0.37 seconds
Started Mar 31 12:35:57 PM PDT 24
Finished Mar 31 12:35:58 PM PDT 24
Peak memory 146356 kb
Host smart-80496a2d-9baf-4117-b10b-b3cde5df527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139034925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3139034925
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3105281779
Short name T5
Test name
Test status
Simulation time 5092825 ps
CPU time 0.39 seconds
Started Mar 31 12:35:55 PM PDT 24
Finished Mar 31 12:35:56 PM PDT 24
Peak memory 146460 kb
Host smart-36638de2-c19b-40bc-a68d-774e9342b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105281779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3105281779
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2493131550
Short name T7
Test name
Test status
Simulation time 4249901 ps
CPU time 0.38 seconds
Started Mar 31 12:35:59 PM PDT 24
Finished Mar 31 12:35:59 PM PDT 24
Peak memory 146460 kb
Host smart-f133e2e7-f8eb-4404-a53c-a9b08ca13379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493131550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2493131550
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1830707938
Short name T3
Test name
Test status
Simulation time 4669412 ps
CPU time 0.41 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:06 PM PDT 24
Peak memory 146456 kb
Host smart-226f0495-8c38-49e4-baa0-010168d17ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830707938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1830707938
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.4193620158
Short name T12
Test name
Test status
Simulation time 4910459 ps
CPU time 0.37 seconds
Started Mar 31 12:36:04 PM PDT 24
Finished Mar 31 12:36:05 PM PDT 24
Peak memory 146492 kb
Host smart-5ee81e0b-c4db-4ce3-b882-dd88abd61a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193620158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4193620158
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.257867349
Short name T11
Test name
Test status
Simulation time 4117497 ps
CPU time 0.36 seconds
Started Mar 31 12:35:55 PM PDT 24
Finished Mar 31 12:35:56 PM PDT 24
Peak memory 146380 kb
Host smart-cc290285-797d-4f7a-afe5-0ca83d5200b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257867349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.257867349
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3370111358
Short name T20
Test name
Test status
Simulation time 4929698 ps
CPU time 0.38 seconds
Started Mar 31 12:35:55 PM PDT 24
Finished Mar 31 12:35:56 PM PDT 24
Peak memory 146412 kb
Host smart-bdb2add8-516b-4baa-9ac1-32f8a90b56da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370111358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3370111358
Directory /workspace/9.prim_esc_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%