| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.4177107274 |
| 88.44 | 2.33 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.661590501 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.3773286096 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.3467302932 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2804266860 |
| /workspace/coverage/default/11.prim_esc_test.1276217408 |
| /workspace/coverage/default/12.prim_esc_test.3493916569 |
| /workspace/coverage/default/13.prim_esc_test.3077818035 |
| /workspace/coverage/default/14.prim_esc_test.3019789357 |
| /workspace/coverage/default/15.prim_esc_test.3729135320 |
| /workspace/coverage/default/16.prim_esc_test.3644984124 |
| /workspace/coverage/default/18.prim_esc_test.1349281734 |
| /workspace/coverage/default/19.prim_esc_test.4038429170 |
| /workspace/coverage/default/2.prim_esc_test.4077369938 |
| /workspace/coverage/default/3.prim_esc_test.182832365 |
| /workspace/coverage/default/5.prim_esc_test.2433267461 |
| /workspace/coverage/default/6.prim_esc_test.3480703279 |
| /workspace/coverage/default/7.prim_esc_test.3305520660 |
| /workspace/coverage/default/8.prim_esc_test.2725146164 |
| /workspace/coverage/default/9.prim_esc_test.3454182627 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_esc_test.3454182627 | Apr 02 12:17:33 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 5190095 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.4177107274 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:27 PM PDT 24 | 5577777 ps | ||
| T3 | /workspace/coverage/default/0.prim_esc_test.2804266860 | Apr 02 12:17:16 PM PDT 24 | Apr 02 12:17:16 PM PDT 24 | 4267090 ps | ||
| T4 | /workspace/coverage/default/16.prim_esc_test.3644984124 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:27 PM PDT 24 | 5024584 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.3305520660 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:27 PM PDT 24 | 4581016 ps | ||
| T9 | /workspace/coverage/default/12.prim_esc_test.3493916569 | Apr 02 12:17:34 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 4472035 ps | ||
| T12 | /workspace/coverage/default/5.prim_esc_test.2433267461 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:26 PM PDT 24 | 5002461 ps | ||
| T15 | /workspace/coverage/default/18.prim_esc_test.1349281734 | Apr 02 12:22:26 PM PDT 24 | Apr 02 12:22:26 PM PDT 24 | 4930292 ps | ||
| T16 | /workspace/coverage/default/15.prim_esc_test.3729135320 | Apr 02 12:17:36 PM PDT 24 | Apr 02 12:17:37 PM PDT 24 | 4580041 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.661590501 | Apr 02 12:17:35 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 4572428 ps | ||
| T17 | /workspace/coverage/default/14.prim_esc_test.3019789357 | Apr 02 12:18:59 PM PDT 24 | Apr 02 12:19:00 PM PDT 24 | 4493214 ps | ||
| T14 | /workspace/coverage/default/6.prim_esc_test.3480703279 | Apr 02 12:17:23 PM PDT 24 | Apr 02 12:17:24 PM PDT 24 | 4802943 ps | ||
| T13 | /workspace/coverage/default/19.prim_esc_test.4038429170 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:27 PM PDT 24 | 4785050 ps | ||
| T5 | /workspace/coverage/default/11.prim_esc_test.1276217408 | Apr 02 12:18:59 PM PDT 24 | Apr 02 12:19:00 PM PDT 24 | 4633200 ps | ||
| T10 | /workspace/coverage/default/3.prim_esc_test.182832365 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:26 PM PDT 24 | 5420941 ps | ||
| T18 | /workspace/coverage/default/13.prim_esc_test.3077818035 | Apr 02 12:17:34 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 4828471 ps | ||
| T19 | /workspace/coverage/default/8.prim_esc_test.2725146164 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 4700684 ps | ||
| T6 | /workspace/coverage/default/10.prim_esc_test.3467302932 | Apr 02 12:17:36 PM PDT 24 | Apr 02 12:17:37 PM PDT 24 | 4690165 ps | ||
| T11 | /workspace/coverage/default/17.prim_esc_test.3773286096 | Apr 02 12:17:34 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 5511161 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.4077369938 | Apr 02 12:17:33 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 5342461 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.4177107274 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5577777 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:27 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-b58dfbfc-b126-4c34-845d-efbf7a172963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177107274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4177107274 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.661590501 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4572428 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:35 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 146424 kb |
| Host | smart-672822f1-fe3d-4cb7-a46c-da2807b14a12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661590501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.661590501 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3773286096 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5511161 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:34 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-9969e110-1810-442a-bd8a-8e18f9137d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773286096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3773286096 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3467302932 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4690165 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:36 PM PDT 24 |
| Finished | Apr 02 12:17:37 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-08b1e9c5-102c-417b-95b9-447054b1b0fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467302932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3467302932 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2804266860 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4267090 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:16 PM PDT 24 |
| Finished | Apr 02 12:17:16 PM PDT 24 |
| Peak memory | 146616 kb |
| Host | smart-fa44bed3-a10d-44be-9008-c68c242ad777 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804266860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2804266860 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1276217408 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4633200 ps |
| CPU time | 0.44 seconds |
| Started | Apr 02 12:18:59 PM PDT 24 |
| Finished | Apr 02 12:19:00 PM PDT 24 |
| Peak memory | 144476 kb |
| Host | smart-55024489-3f11-439c-8d8e-4a8f39abfd16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276217408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1276217408 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3493916569 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4472035 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:34 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-2f7460fa-d22c-4db9-8536-2dcb94c7be1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493916569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3493916569 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3077818035 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4828471 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:34 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-21eeeb65-0401-4479-a53a-b3cb083b388d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077818035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3077818035 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3019789357 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4493214 ps |
| CPU time | 0.5 seconds |
| Started | Apr 02 12:18:59 PM PDT 24 |
| Finished | Apr 02 12:19:00 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-1e89cfb1-3cd2-4eab-b0f3-a7665fdd5da4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3019789357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3019789357 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3729135320 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4580041 ps |
| CPU time | 0.37 seconds |
| Started | Apr 02 12:17:36 PM PDT 24 |
| Finished | Apr 02 12:17:37 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-09db30e7-98d1-4491-9434-410880f3f7d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729135320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3729135320 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3644984124 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5024584 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:27 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-9bd8f3ba-cef0-4662-94e8-af3357136c45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644984124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3644984124 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1349281734 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4930292 ps |
| CPU time | 0.36 seconds |
| Started | Apr 02 12:22:26 PM PDT 24 |
| Finished | Apr 02 12:22:26 PM PDT 24 |
| Peak memory | 145948 kb |
| Host | smart-0c6adf0f-01d1-466c-9429-5e3ee5c338b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349281734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1349281734 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.4038429170 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4785050 ps |
| CPU time | 0.36 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:27 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-56e12739-3888-4733-ba02-18609fb46b1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038429170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4038429170 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.4077369938 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5342461 ps |
| CPU time | 0.35 seconds |
| Started | Apr 02 12:17:33 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 146056 kb |
| Host | smart-c20c5107-3255-452b-a6d9-a1b2abff7bed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077369938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4077369938 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.182832365 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5420941 ps |
| CPU time | 0.37 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:26 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-3d3d8a1f-8ddf-430e-8dd9-1b18d9d81359 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182832365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.182832365 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2433267461 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5002461 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:26 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-6698942a-07fc-4cc0-b206-2c3d8bbcda73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433267461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2433267461 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3480703279 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4802943 ps |
| CPU time | 0.37 seconds |
| Started | Apr 02 12:17:23 PM PDT 24 |
| Finished | Apr 02 12:17:24 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-23a12e02-56d9-41d9-8236-051b44cd7957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480703279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3480703279 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3305520660 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4581016 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:27 PM PDT 24 |
| Peak memory | 146264 kb |
| Host | smart-af8c6c82-f777-45f4-93f3-bf7319016f22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305520660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3305520660 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2725146164 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4700684 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 146400 kb |
| Host | smart-4021b526-2d6f-4c55-ac12-e375d42048f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725146164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2725146164 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3454182627 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5190095 ps |
| CPU time | 0.36 seconds |
| Started | Apr 02 12:17:33 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 146400 kb |
| Host | smart-2e5f8872-1195-4621-bc13-31ebb20ea211 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454182627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3454182627 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |