| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 88.87 | 92.38 | 86.36 | 100.00 | 89.29 | 83.72 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.02 | 85.02 | 90.48 | 90.48 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.1591003298 |
| 87.14 | 2.12 | 91.43 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 82.14 | 7.14 | 81.40 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.1195666983 |
| 88.28 | 1.14 | 92.38 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.1767814002 |
| 88.87 | 0.60 | 92.38 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 83.72 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.682598125 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1873496370 |
| /workspace/coverage/default/10.prim_esc_test.504412272 |
| /workspace/coverage/default/11.prim_esc_test.27444994 |
| /workspace/coverage/default/13.prim_esc_test.4265870138 |
| /workspace/coverage/default/14.prim_esc_test.1366669125 |
| /workspace/coverage/default/16.prim_esc_test.792032532 |
| /workspace/coverage/default/17.prim_esc_test.3254087260 |
| /workspace/coverage/default/18.prim_esc_test.4100052611 |
| /workspace/coverage/default/19.prim_esc_test.4211705791 |
| /workspace/coverage/default/2.prim_esc_test.3943243734 |
| /workspace/coverage/default/3.prim_esc_test.2544873994 |
| /workspace/coverage/default/5.prim_esc_test.1918277962 |
| /workspace/coverage/default/6.prim_esc_test.225012131 |
| /workspace/coverage/default/7.prim_esc_test.3484407763 |
| /workspace/coverage/default/8.prim_esc_test.396940971 |
| /workspace/coverage/default/9.prim_esc_test.4070030341 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_esc_test.1591003298 | Apr 04 02:02:48 PM PDT 24 | Apr 04 02:02:48 PM PDT 24 | 4832672 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.3943243734 | Apr 04 02:02:44 PM PDT 24 | Apr 04 02:02:45 PM PDT 24 | 4368619 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.504412272 | Apr 04 02:03:01 PM PDT 24 | Apr 04 02:03:05 PM PDT 24 | 4682380 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.2544873994 | Apr 04 02:02:46 PM PDT 24 | Apr 04 02:02:47 PM PDT 24 | 5125440 ps | ||
| T9 | /workspace/coverage/default/6.prim_esc_test.225012131 | Apr 04 02:02:43 PM PDT 24 | Apr 04 02:02:44 PM PDT 24 | 4371604 ps | ||
| T10 | /workspace/coverage/default/18.prim_esc_test.4100052611 | Apr 04 02:03:00 PM PDT 24 | Apr 04 02:03:05 PM PDT 24 | 4978480 ps | ||
| T6 | /workspace/coverage/default/13.prim_esc_test.4265870138 | Apr 04 02:03:00 PM PDT 24 | Apr 04 02:03:05 PM PDT 24 | 4839735 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.3484407763 | Apr 04 02:02:48 PM PDT 24 | Apr 04 02:02:48 PM PDT 24 | 4733161 ps | ||
| T11 | /workspace/coverage/default/9.prim_esc_test.4070030341 | Apr 04 02:02:46 PM PDT 24 | Apr 04 02:02:46 PM PDT 24 | 4538432 ps | ||
| T12 | /workspace/coverage/default/8.prim_esc_test.396940971 | Apr 04 02:02:48 PM PDT 24 | Apr 04 02:02:48 PM PDT 24 | 4663437 ps | ||
| T4 | /workspace/coverage/default/12.prim_esc_test.682598125 | Apr 04 02:02:59 PM PDT 24 | Apr 04 02:03:04 PM PDT 24 | 5049609 ps | ||
| T5 | /workspace/coverage/default/15.prim_esc_test.1195666983 | Apr 04 02:02:59 PM PDT 24 | Apr 04 02:03:04 PM PDT 24 | 4676878 ps | ||
| T13 | /workspace/coverage/default/16.prim_esc_test.792032532 | Apr 04 02:03:04 PM PDT 24 | Apr 04 02:03:07 PM PDT 24 | 4587775 ps | ||
| T17 | /workspace/coverage/default/0.prim_esc_test.1873496370 | Apr 04 02:02:47 PM PDT 24 | Apr 04 02:02:48 PM PDT 24 | 4733555 ps | ||
| T14 | /workspace/coverage/default/5.prim_esc_test.1918277962 | Apr 04 02:02:47 PM PDT 24 | Apr 04 02:02:48 PM PDT 24 | 4862022 ps | ||
| T15 | /workspace/coverage/default/17.prim_esc_test.3254087260 | Apr 04 02:03:02 PM PDT 24 | Apr 04 02:03:05 PM PDT 24 | 5170341 ps | ||
| T18 | /workspace/coverage/default/19.prim_esc_test.4211705791 | Apr 04 02:03:00 PM PDT 24 | Apr 04 02:03:05 PM PDT 24 | 5225739 ps | ||
| T16 | /workspace/coverage/default/4.prim_esc_test.1767814002 | Apr 04 02:02:45 PM PDT 24 | Apr 04 02:02:46 PM PDT 24 | 4355534 ps | ||
| T19 | /workspace/coverage/default/11.prim_esc_test.27444994 | Apr 04 02:02:58 PM PDT 24 | Apr 04 02:03:04 PM PDT 24 | 4648180 ps | ||
| T20 | /workspace/coverage/default/14.prim_esc_test.1366669125 | Apr 04 02:02:59 PM PDT 24 | Apr 04 02:03:04 PM PDT 24 | 5272556 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.1591003298 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4832672 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:02:48 PM PDT 24 |
| Finished | Apr 04 02:02:48 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-ef4ac6bd-7389-419f-9023-c596c5a28c2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591003298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1591003298 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1195666983 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4676878 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:02:59 PM PDT 24 |
| Finished | Apr 04 02:03:04 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-1b4fe565-3fa5-4db7-923a-aa9786166914 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195666983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1195666983 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1767814002 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4355534 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:02:45 PM PDT 24 |
| Finished | Apr 04 02:02:46 PM PDT 24 |
| Peak memory | 146496 kb |
| Host | smart-f7df79c4-8b9f-4513-8821-c445d2978284 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767814002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1767814002 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.682598125 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5049609 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:02:59 PM PDT 24 |
| Finished | Apr 04 02:03:04 PM PDT 24 |
| Peak memory | 146408 kb |
| Host | smart-2b7e8d16-1d35-4d2a-b37f-36c1d42593e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682598125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.682598125 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1873496370 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4733555 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:02:47 PM PDT 24 |
| Finished | Apr 04 02:02:48 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-4effbcca-909e-417b-8562-1419417c1595 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873496370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1873496370 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.504412272 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4682380 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:03:01 PM PDT 24 |
| Finished | Apr 04 02:03:05 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-fb134f5a-e6d5-4bfd-997d-10e23640ec28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504412272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.504412272 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.27444994 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4648180 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 02:02:58 PM PDT 24 |
| Finished | Apr 04 02:03:04 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-c7df3a16-e49c-40c3-95c0-7b9fc9c9bc66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27444994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.27444994 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4265870138 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4839735 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:03:00 PM PDT 24 |
| Finished | Apr 04 02:03:05 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-e16aa5e1-20c5-4b9e-8f08-6812ec610e6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265870138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4265870138 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1366669125 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5272556 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:02:59 PM PDT 24 |
| Finished | Apr 04 02:03:04 PM PDT 24 |
| Peak memory | 146480 kb |
| Host | smart-032234e6-8ffa-4119-96b8-b4074719aeef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366669125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1366669125 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.792032532 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4587775 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:03:04 PM PDT 24 |
| Finished | Apr 04 02:03:07 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-76c79057-e5af-4d88-bafe-fb49da78c70a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792032532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.792032532 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3254087260 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5170341 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:03:02 PM PDT 24 |
| Finished | Apr 04 02:03:05 PM PDT 24 |
| Peak memory | 146496 kb |
| Host | smart-80d33288-de59-4adc-ba9d-c9f457b94d6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254087260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3254087260 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.4100052611 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4978480 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 02:03:00 PM PDT 24 |
| Finished | Apr 04 02:03:05 PM PDT 24 |
| Peak memory | 146420 kb |
| Host | smart-918c3814-b64d-4e82-a684-ce215dafc247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100052611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.4100052611 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.4211705791 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5225739 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:03:00 PM PDT 24 |
| Finished | Apr 04 02:03:05 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-0eb9ab7b-376f-4b7d-9e44-70f3f4b20837 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211705791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4211705791 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3943243734 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4368619 ps |
| CPU time | 0.36 seconds |
| Started | Apr 04 02:02:44 PM PDT 24 |
| Finished | Apr 04 02:02:45 PM PDT 24 |
| Peak memory | 146484 kb |
| Host | smart-276eaf2c-0309-4573-bbc9-0fe9f20e7673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943243734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3943243734 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2544873994 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5125440 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:02:46 PM PDT 24 |
| Finished | Apr 04 02:02:47 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-54fb1e18-6168-49f5-9dd5-5863d2d38d58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544873994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2544873994 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1918277962 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4862022 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:02:47 PM PDT 24 |
| Finished | Apr 04 02:02:48 PM PDT 24 |
| Peak memory | 146568 kb |
| Host | smart-12c76886-6d65-4d1f-9c85-2085aac845ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918277962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1918277962 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.225012131 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4371604 ps |
| CPU time | 0.36 seconds |
| Started | Apr 04 02:02:43 PM PDT 24 |
| Finished | Apr 04 02:02:44 PM PDT 24 |
| Peak memory | 146416 kb |
| Host | smart-08946d33-efb6-4cc5-9857-f6af948da42d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225012131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.225012131 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3484407763 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4733161 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 02:02:48 PM PDT 24 |
| Finished | Apr 04 02:02:48 PM PDT 24 |
| Peak memory | 146484 kb |
| Host | smart-c478da1f-d777-439d-991c-315d3489b977 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484407763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3484407763 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.396940971 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4663437 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 02:02:48 PM PDT 24 |
| Finished | Apr 04 02:02:48 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-134ef970-d7a5-42bb-856b-01ca9cdacad3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396940971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.396940971 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.4070030341 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4538432 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:02:46 PM PDT 24 |
| Finished | Apr 04 02:02:46 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-b89553ba-e2ad-46ac-9127-e8c1e5c5d1b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070030341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4070030341 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |