| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.56 | 85.56 | 92.38 | 92.38 | 79.55 | 79.55 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/13.prim_esc_test.2926943039 |
| 89.03 | 3.47 | 93.33 | 0.95 | 86.36 | 6.82 | 100.00 | 0.00 | 89.29 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.877241708 |
| 90.17 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.331745541 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.1174673381 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.54086042 |
| /workspace/coverage/default/10.prim_esc_test.722307672 |
| /workspace/coverage/default/11.prim_esc_test.2654798715 |
| /workspace/coverage/default/12.prim_esc_test.2533015873 |
| /workspace/coverage/default/14.prim_esc_test.352093964 |
| /workspace/coverage/default/15.prim_esc_test.2541155061 |
| /workspace/coverage/default/18.prim_esc_test.818590003 |
| /workspace/coverage/default/19.prim_esc_test.643676933 |
| /workspace/coverage/default/2.prim_esc_test.136954906 |
| /workspace/coverage/default/3.prim_esc_test.1987619369 |
| /workspace/coverage/default/4.prim_esc_test.3205337134 |
| /workspace/coverage/default/5.prim_esc_test.535467028 |
| /workspace/coverage/default/6.prim_esc_test.2235209870 |
| /workspace/coverage/default/7.prim_esc_test.2814627124 |
| /workspace/coverage/default/8.prim_esc_test.939036913 |
| /workspace/coverage/default/9.prim_esc_test.3152313660 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_esc_test.877241708 | Apr 15 12:30:31 PM PDT 24 | Apr 15 12:30:33 PM PDT 24 | 5057428 ps | ||
| T2 | /workspace/coverage/default/17.prim_esc_test.1174673381 | Apr 15 12:30:29 PM PDT 24 | Apr 15 12:30:30 PM PDT 24 | 4742611 ps | ||
| T3 | /workspace/coverage/default/12.prim_esc_test.2533015873 | Apr 15 12:30:31 PM PDT 24 | Apr 15 12:30:33 PM PDT 24 | 4709503 ps | ||
| T4 | /workspace/coverage/default/2.prim_esc_test.136954906 | Apr 15 12:30:30 PM PDT 24 | Apr 15 12:30:31 PM PDT 24 | 4636673 ps | ||
| T9 | /workspace/coverage/default/0.prim_esc_test.331745541 | Apr 15 12:30:35 PM PDT 24 | Apr 15 12:30:37 PM PDT 24 | 4636178 ps | ||
| T10 | /workspace/coverage/default/15.prim_esc_test.2541155061 | Apr 15 12:30:32 PM PDT 24 | Apr 15 12:30:44 PM PDT 24 | 4469248 ps | ||
| T12 | /workspace/coverage/default/11.prim_esc_test.2654798715 | Apr 15 12:30:26 PM PDT 24 | Apr 15 12:30:27 PM PDT 24 | 4556305 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.535467028 | Apr 15 12:30:35 PM PDT 24 | Apr 15 12:30:37 PM PDT 24 | 4992185 ps | ||
| T6 | /workspace/coverage/default/13.prim_esc_test.2926943039 | Apr 15 12:30:36 PM PDT 24 | Apr 15 12:30:38 PM PDT 24 | 4700904 ps | ||
| T13 | /workspace/coverage/default/4.prim_esc_test.3205337134 | Apr 15 12:30:33 PM PDT 24 | Apr 15 12:30:34 PM PDT 24 | 4800758 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.1987619369 | Apr 15 12:30:31 PM PDT 24 | Apr 15 12:30:33 PM PDT 24 | 4663935 ps | ||
| T11 | /workspace/coverage/default/14.prim_esc_test.352093964 | Apr 15 12:30:29 PM PDT 24 | Apr 15 12:30:31 PM PDT 24 | 5358717 ps | ||
| T5 | /workspace/coverage/default/7.prim_esc_test.2814627124 | Apr 15 12:30:29 PM PDT 24 | Apr 15 12:30:30 PM PDT 24 | 4879053 ps | ||
| T16 | /workspace/coverage/default/10.prim_esc_test.722307672 | Apr 15 12:30:31 PM PDT 24 | Apr 15 12:30:33 PM PDT 24 | 4687178 ps | ||
| T17 | /workspace/coverage/default/1.prim_esc_test.54086042 | Apr 15 12:30:37 PM PDT 24 | Apr 15 12:30:39 PM PDT 24 | 5099159 ps | ||
| T7 | /workspace/coverage/default/6.prim_esc_test.2235209870 | Apr 15 12:30:30 PM PDT 24 | Apr 15 12:30:31 PM PDT 24 | 4600287 ps | ||
| T14 | /workspace/coverage/default/19.prim_esc_test.643676933 | Apr 15 12:30:36 PM PDT 24 | Apr 15 12:30:37 PM PDT 24 | 4549324 ps | ||
| T18 | /workspace/coverage/default/9.prim_esc_test.3152313660 | Apr 15 12:30:33 PM PDT 24 | Apr 15 12:30:35 PM PDT 24 | 4928004 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.818590003 | Apr 15 12:30:34 PM PDT 24 | Apr 15 12:30:36 PM PDT 24 | 4994471 ps | ||
| T20 | /workspace/coverage/default/8.prim_esc_test.939036913 | Apr 15 12:30:30 PM PDT 24 | Apr 15 12:30:31 PM PDT 24 | 4707603 ps |
| Test location | /workspace/coverage/default/13.prim_esc_test.2926943039 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4700904 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:30:36 PM PDT 24 |
| Finished | Apr 15 12:30:38 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-e901351f-7f5a-45da-bb02-65c8c52e2b40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926943039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2926943039 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.877241708 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5057428 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:30:31 PM PDT 24 |
| Finished | Apr 15 12:30:33 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-8cd65491-727c-4196-af75-59c476dab7c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877241708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.877241708 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.331745541 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4636178 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:30:35 PM PDT 24 |
| Finished | Apr 15 12:30:37 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-2e2deab0-1f2a-41ac-8771-a6c41e24e871 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331745541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.331745541 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1174673381 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4742611 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:30:29 PM PDT 24 |
| Finished | Apr 15 12:30:30 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-b0500508-8af6-4e08-b50e-ffd9ccdad413 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174673381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1174673381 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.54086042 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5099159 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:30:37 PM PDT 24 |
| Finished | Apr 15 12:30:39 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-0e84cb95-e8b5-4457-8d90-80b7ea83e305 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54086042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.54086042 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.722307672 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4687178 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:31 PM PDT 24 |
| Finished | Apr 15 12:30:33 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-cfd2affc-0b7e-4e99-9dc6-490d70bd5760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722307672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.722307672 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2654798715 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4556305 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:30:26 PM PDT 24 |
| Finished | Apr 15 12:30:27 PM PDT 24 |
| Peak memory | 146400 kb |
| Host | smart-aa3a5c07-81b0-4b2f-ae0b-0342f89321c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654798715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2654798715 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2533015873 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4709503 ps |
| CPU time | 0.36 seconds |
| Started | Apr 15 12:30:31 PM PDT 24 |
| Finished | Apr 15 12:30:33 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-f659cd6f-9dcd-404d-a20d-79453ad9cd06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533015873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2533015873 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.352093964 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5358717 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:29 PM PDT 24 |
| Finished | Apr 15 12:30:31 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-ef8a4cac-8092-46e1-a8ab-362e57dedf1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352093964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.352093964 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2541155061 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4469248 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:30:32 PM PDT 24 |
| Finished | Apr 15 12:30:44 PM PDT 24 |
| Peak memory | 146484 kb |
| Host | smart-bb6c7b91-cc2a-4868-9df9-b4407f32e7b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541155061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2541155061 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.818590003 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4994471 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:34 PM PDT 24 |
| Finished | Apr 15 12:30:36 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-07b90a9a-3519-4867-97d6-935834cfe3aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818590003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.818590003 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.643676933 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4549324 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:36 PM PDT 24 |
| Finished | Apr 15 12:30:37 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-2af13a20-669b-4c3a-9cee-fb2ed27f560b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643676933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.643676933 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.136954906 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4636673 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:30:30 PM PDT 24 |
| Finished | Apr 15 12:30:31 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-99013b7e-8840-491d-b413-50b2fa76a61e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136954906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.136954906 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1987619369 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4663935 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:31 PM PDT 24 |
| Finished | Apr 15 12:30:33 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-004469cd-29a0-4bdc-ae73-e28cc8f708e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987619369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1987619369 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3205337134 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4800758 ps |
| CPU time | 0.35 seconds |
| Started | Apr 15 12:30:33 PM PDT 24 |
| Finished | Apr 15 12:30:34 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-dd286cdf-d979-4f73-b327-1da96b9cc2ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205337134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3205337134 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.535467028 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4992185 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:30:35 PM PDT 24 |
| Finished | Apr 15 12:30:37 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-97efbdfa-b765-4c12-a95c-6a383df2287b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535467028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.535467028 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2235209870 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4600287 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:30 PM PDT 24 |
| Finished | Apr 15 12:30:31 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-089cef98-483d-4bd9-843d-7b47b7fb79ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235209870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2235209870 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2814627124 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4879053 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:30:29 PM PDT 24 |
| Finished | Apr 15 12:30:30 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-c75ddff4-ccec-4f64-8776-dc76cd8f8621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814627124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2814627124 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.939036913 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4707603 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:30:30 PM PDT 24 |
| Finished | Apr 15 12:30:31 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-96ff0c1c-30aa-4003-855b-3cab17aa5842 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939036913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.939036913 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3152313660 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4928004 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:30:33 PM PDT 24 |
| Finished | Apr 15 12:30:35 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-9ecb417d-0dd4-4182-865d-8e819b551ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152313660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3152313660 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |