| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.32 | 86.32 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/3.prim_esc_test.3244511100 |
| 88.44 | 2.12 | 93.33 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.3291535673 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1981371641 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.1613622595 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1366388670 |
| /workspace/coverage/default/1.prim_esc_test.3166123592 |
| /workspace/coverage/default/12.prim_esc_test.2065319041 |
| /workspace/coverage/default/13.prim_esc_test.1161340230 |
| /workspace/coverage/default/15.prim_esc_test.2028914326 |
| /workspace/coverage/default/16.prim_esc_test.489075175 |
| /workspace/coverage/default/17.prim_esc_test.939764475 |
| /workspace/coverage/default/18.prim_esc_test.18516146 |
| /workspace/coverage/default/19.prim_esc_test.3927924847 |
| /workspace/coverage/default/2.prim_esc_test.310948230 |
| /workspace/coverage/default/4.prim_esc_test.626791077 |
| /workspace/coverage/default/5.prim_esc_test.1220471389 |
| /workspace/coverage/default/6.prim_esc_test.3861973885 |
| /workspace/coverage/default/7.prim_esc_test.4095007593 |
| /workspace/coverage/default/8.prim_esc_test.3921110464 |
| /workspace/coverage/default/9.prim_esc_test.728910281 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_esc_test.3166123592 | Apr 16 12:21:48 PM PDT 24 | Apr 16 12:21:51 PM PDT 24 | 5248179 ps | ||
| T2 | /workspace/coverage/default/5.prim_esc_test.1220471389 | Apr 16 12:17:11 PM PDT 24 | Apr 16 12:17:13 PM PDT 24 | 4987373 ps | ||
| T3 | /workspace/coverage/default/9.prim_esc_test.728910281 | Apr 16 12:17:20 PM PDT 24 | Apr 16 12:17:21 PM PDT 24 | 4198938 ps | ||
| T5 | /workspace/coverage/default/12.prim_esc_test.2065319041 | Apr 16 12:17:08 PM PDT 24 | Apr 16 12:17:10 PM PDT 24 | 5428984 ps | ||
| T4 | /workspace/coverage/default/11.prim_esc_test.1613622595 | Apr 16 12:17:42 PM PDT 24 | Apr 16 12:17:43 PM PDT 24 | 4695378 ps | ||
| T6 | /workspace/coverage/default/8.prim_esc_test.3921110464 | Apr 16 12:17:16 PM PDT 24 | Apr 16 12:17:18 PM PDT 24 | 4556607 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.3244511100 | Apr 16 12:16:51 PM PDT 24 | Apr 16 12:16:53 PM PDT 24 | 4664518 ps | ||
| T14 | /workspace/coverage/default/6.prim_esc_test.3861973885 | Apr 16 12:17:17 PM PDT 24 | Apr 16 12:17:18 PM PDT 24 | 4660603 ps | ||
| T10 | /workspace/coverage/default/7.prim_esc_test.4095007593 | Apr 16 12:17:17 PM PDT 24 | Apr 16 12:17:18 PM PDT 24 | 5085165 ps | ||
| T15 | /workspace/coverage/default/19.prim_esc_test.3927924847 | Apr 16 12:22:48 PM PDT 24 | Apr 16 12:22:53 PM PDT 24 | 4321008 ps | ||
| T16 | /workspace/coverage/default/15.prim_esc_test.2028914326 | Apr 16 12:21:06 PM PDT 24 | Apr 16 12:21:08 PM PDT 24 | 4984915 ps | ||
| T7 | /workspace/coverage/default/14.prim_esc_test.3291535673 | Apr 16 12:20:59 PM PDT 24 | Apr 16 12:21:01 PM PDT 24 | 4976344 ps | ||
| T17 | /workspace/coverage/default/13.prim_esc_test.1161340230 | Apr 16 12:18:50 PM PDT 24 | Apr 16 12:18:52 PM PDT 24 | 4952037 ps | ||
| T18 | /workspace/coverage/default/0.prim_esc_test.1366388670 | Apr 16 12:21:48 PM PDT 24 | Apr 16 12:21:51 PM PDT 24 | 4705554 ps | ||
| T13 | /workspace/coverage/default/18.prim_esc_test.18516146 | Apr 16 12:17:19 PM PDT 24 | Apr 16 12:17:20 PM PDT 24 | 4624319 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.626791077 | Apr 16 12:17:15 PM PDT 24 | Apr 16 12:17:16 PM PDT 24 | 5130853 ps | ||
| T11 | /workspace/coverage/default/10.prim_esc_test.1981371641 | Apr 16 12:18:06 PM PDT 24 | Apr 16 12:18:07 PM PDT 24 | 4641376 ps | ||
| T19 | /workspace/coverage/default/17.prim_esc_test.939764475 | Apr 16 12:21:09 PM PDT 24 | Apr 16 12:21:11 PM PDT 24 | 4695364 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.489075175 | Apr 16 12:17:18 PM PDT 24 | Apr 16 12:17:19 PM PDT 24 | 4928305 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.310948230 | Apr 16 12:22:39 PM PDT 24 | Apr 16 12:22:44 PM PDT 24 | 4839602 ps |
| Test location | /workspace/coverage/default/3.prim_esc_test.3244511100 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4664518 ps |
| CPU time | 0.4 seconds |
| Started | Apr 16 12:16:51 PM PDT 24 |
| Finished | Apr 16 12:16:53 PM PDT 24 |
| Peak memory | 146072 kb |
| Host | smart-e9cf78bf-ea2a-4fcb-b1a2-6edf140f0943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244511100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3244511100 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3291535673 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4976344 ps |
| CPU time | 0.41 seconds |
| Started | Apr 16 12:20:59 PM PDT 24 |
| Finished | Apr 16 12:21:01 PM PDT 24 |
| Peak memory | 144800 kb |
| Host | smart-a9a30d9b-7268-43bf-b52e-ea017da66d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291535673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3291535673 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1981371641 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4641376 ps |
| CPU time | 0.38 seconds |
| Started | Apr 16 12:18:06 PM PDT 24 |
| Finished | Apr 16 12:18:07 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-d452274a-1c81-4ace-9198-b717734ee2d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981371641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1981371641 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1613622595 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4695378 ps |
| CPU time | 0.39 seconds |
| Started | Apr 16 12:17:42 PM PDT 24 |
| Finished | Apr 16 12:17:43 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-7f737f7b-2cf9-49d2-8df4-b5a46bb74b3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613622595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1613622595 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1366388670 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4705554 ps |
| CPU time | 0.38 seconds |
| Started | Apr 16 12:21:48 PM PDT 24 |
| Finished | Apr 16 12:21:51 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-01cb009e-febd-407d-94bc-b781397712ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366388670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1366388670 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3166123592 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5248179 ps |
| CPU time | 0.42 seconds |
| Started | Apr 16 12:21:48 PM PDT 24 |
| Finished | Apr 16 12:21:51 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-4173aea3-67bc-478a-b08b-63abb37cd825 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166123592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3166123592 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2065319041 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5428984 ps |
| CPU time | 0.37 seconds |
| Started | Apr 16 12:17:08 PM PDT 24 |
| Finished | Apr 16 12:17:10 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-18fd1818-d4f8-43dd-a571-7c8108699faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2065319041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2065319041 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1161340230 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4952037 ps |
| CPU time | 0.4 seconds |
| Started | Apr 16 12:18:50 PM PDT 24 |
| Finished | Apr 16 12:18:52 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-76410ebf-f7e6-4bb2-9abc-1e7278d57c18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161340230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1161340230 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2028914326 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4984915 ps |
| CPU time | 0.41 seconds |
| Started | Apr 16 12:21:06 PM PDT 24 |
| Finished | Apr 16 12:21:08 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-7e2bcf10-8e55-422c-906f-940d04e13df6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028914326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2028914326 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.489075175 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4928305 ps |
| CPU time | 0.39 seconds |
| Started | Apr 16 12:17:18 PM PDT 24 |
| Finished | Apr 16 12:17:19 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-5ba88660-570c-4688-a8dc-9b5106d2803f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489075175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.489075175 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.939764475 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4695364 ps |
| CPU time | 0.4 seconds |
| Started | Apr 16 12:21:09 PM PDT 24 |
| Finished | Apr 16 12:21:11 PM PDT 24 |
| Peak memory | 145956 kb |
| Host | smart-25768c30-de81-4dd4-9fe5-894add84f4b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939764475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.939764475 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.18516146 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4624319 ps |
| CPU time | 0.39 seconds |
| Started | Apr 16 12:17:19 PM PDT 24 |
| Finished | Apr 16 12:17:20 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-6e392498-2146-4949-b708-4398f56295b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18516146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.18516146 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3927924847 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4321008 ps |
| CPU time | 0.36 seconds |
| Started | Apr 16 12:22:48 PM PDT 24 |
| Finished | Apr 16 12:22:53 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-bcfecd8f-1db8-4771-ac6a-f9251d24a47a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3927924847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3927924847 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.310948230 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4839602 ps |
| CPU time | 0.37 seconds |
| Started | Apr 16 12:22:39 PM PDT 24 |
| Finished | Apr 16 12:22:44 PM PDT 24 |
| Peak memory | 146288 kb |
| Host | smart-c66d9f70-0aca-4631-80a2-81c74a3cdbdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310948230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.310948230 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.626791077 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5130853 ps |
| CPU time | 0.39 seconds |
| Started | Apr 16 12:17:15 PM PDT 24 |
| Finished | Apr 16 12:17:16 PM PDT 24 |
| Peak memory | 146564 kb |
| Host | smart-cb95b836-b05d-464d-8fdf-713e40c3f928 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626791077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.626791077 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1220471389 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4987373 ps |
| CPU time | 0.39 seconds |
| Started | Apr 16 12:17:11 PM PDT 24 |
| Finished | Apr 16 12:17:13 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-885985a4-5745-49f7-bab7-d4d11668ba1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220471389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1220471389 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3861973885 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4660603 ps |
| CPU time | 0.38 seconds |
| Started | Apr 16 12:17:17 PM PDT 24 |
| Finished | Apr 16 12:17:18 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-031a9012-82a7-4bf3-82f8-4695a33c538d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861973885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3861973885 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4095007593 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5085165 ps |
| CPU time | 0.41 seconds |
| Started | Apr 16 12:17:17 PM PDT 24 |
| Finished | Apr 16 12:17:18 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-8ccb1776-1abc-4003-a6ba-9430b09bd8cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095007593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4095007593 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3921110464 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4556607 ps |
| CPU time | 0.38 seconds |
| Started | Apr 16 12:17:16 PM PDT 24 |
| Finished | Apr 16 12:17:18 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-68ecc86a-3391-4446-a2c4-58a56b65c79c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921110464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3921110464 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.728910281 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4198938 ps |
| CPU time | 0.39 seconds |
| Started | Apr 16 12:17:20 PM PDT 24 |
| Finished | Apr 16 12:17:21 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-415cf7d8-6673-496a-bc2a-e1bac76680d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728910281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.728910281 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |