| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.40 | 85.40 | 90.48 | 90.48 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/5.prim_esc_test.2679970355 |
| 88.44 | 3.04 | 93.33 | 2.86 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.599623065 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.3047370118 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2984250373 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.24360997 |
| /workspace/coverage/default/1.prim_esc_test.1999501987 |
| /workspace/coverage/default/10.prim_esc_test.946451445 |
| /workspace/coverage/default/12.prim_esc_test.1758201998 |
| /workspace/coverage/default/13.prim_esc_test.3238163310 |
| /workspace/coverage/default/14.prim_esc_test.1859760025 |
| /workspace/coverage/default/15.prim_esc_test.1276470103 |
| /workspace/coverage/default/16.prim_esc_test.3986711143 |
| /workspace/coverage/default/17.prim_esc_test.1705293534 |
| /workspace/coverage/default/18.prim_esc_test.3409479192 |
| /workspace/coverage/default/19.prim_esc_test.2569463075 |
| /workspace/coverage/default/2.prim_esc_test.2817360876 |
| /workspace/coverage/default/3.prim_esc_test.2335362985 |
| /workspace/coverage/default/4.prim_esc_test.3422408266 |
| /workspace/coverage/default/6.prim_esc_test.4218155831 |
| /workspace/coverage/default/8.prim_esc_test.3357576714 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_esc_test.2817360876 | Apr 18 01:34:35 PM PDT 24 | Apr 18 01:34:36 PM PDT 24 | 5397822 ps | ||
| T2 | /workspace/coverage/default/15.prim_esc_test.1276470103 | Apr 18 01:34:22 PM PDT 24 | Apr 18 01:34:24 PM PDT 24 | 4643580 ps | ||
| T3 | /workspace/coverage/default/5.prim_esc_test.2679970355 | Apr 18 01:34:12 PM PDT 24 | Apr 18 01:34:14 PM PDT 24 | 5336678 ps | ||
| T4 | /workspace/coverage/default/12.prim_esc_test.1758201998 | Apr 18 01:34:02 PM PDT 24 | Apr 18 01:34:03 PM PDT 24 | 4692031 ps | ||
| T11 | /workspace/coverage/default/1.prim_esc_test.1999501987 | Apr 18 01:34:15 PM PDT 24 | Apr 18 01:34:16 PM PDT 24 | 4541647 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.3047370118 | Apr 18 01:33:57 PM PDT 24 | Apr 18 01:33:58 PM PDT 24 | 5034357 ps | ||
| T9 | /workspace/coverage/default/17.prim_esc_test.1705293534 | Apr 18 01:34:00 PM PDT 24 | Apr 18 01:34:01 PM PDT 24 | 4974440 ps | ||
| T8 | /workspace/coverage/default/19.prim_esc_test.2569463075 | Apr 18 01:34:16 PM PDT 24 | Apr 18 01:34:16 PM PDT 24 | 4404268 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.3986711143 | Apr 18 01:34:06 PM PDT 24 | Apr 18 01:34:08 PM PDT 24 | 4599215 ps | ||
| T10 | /workspace/coverage/default/8.prim_esc_test.3357576714 | Apr 18 01:33:59 PM PDT 24 | Apr 18 01:33:59 PM PDT 24 | 4894717 ps | ||
| T5 | /workspace/coverage/default/6.prim_esc_test.4218155831 | Apr 18 01:34:05 PM PDT 24 | Apr 18 01:34:06 PM PDT 24 | 4664466 ps | ||
| T13 | /workspace/coverage/default/10.prim_esc_test.946451445 | Apr 18 01:34:02 PM PDT 24 | Apr 18 01:34:02 PM PDT 24 | 4852806 ps | ||
| T14 | /workspace/coverage/default/13.prim_esc_test.3238163310 | Apr 18 01:34:07 PM PDT 24 | Apr 18 01:34:08 PM PDT 24 | 5335911 ps | ||
| T6 | /workspace/coverage/default/9.prim_esc_test.599623065 | Apr 18 01:34:13 PM PDT 24 | Apr 18 01:34:14 PM PDT 24 | 4923347 ps | ||
| T15 | /workspace/coverage/default/0.prim_esc_test.24360997 | Apr 18 01:33:56 PM PDT 24 | Apr 18 01:33:58 PM PDT 24 | 4332249 ps | ||
| T16 | /workspace/coverage/default/4.prim_esc_test.3422408266 | Apr 18 01:34:04 PM PDT 24 | Apr 18 01:34:05 PM PDT 24 | 4631978 ps | ||
| T17 | /workspace/coverage/default/14.prim_esc_test.1859760025 | Apr 18 01:34:06 PM PDT 24 | Apr 18 01:34:07 PM PDT 24 | 4259625 ps | ||
| T18 | /workspace/coverage/default/11.prim_esc_test.2984250373 | Apr 18 01:34:06 PM PDT 24 | Apr 18 01:34:07 PM PDT 24 | 4595795 ps | ||
| T19 | /workspace/coverage/default/3.prim_esc_test.2335362985 | Apr 18 01:33:53 PM PDT 24 | Apr 18 01:33:54 PM PDT 24 | 5112860 ps | ||
| T20 | /workspace/coverage/default/18.prim_esc_test.3409479192 | Apr 18 01:34:20 PM PDT 24 | Apr 18 01:34:21 PM PDT 24 | 5046748 ps |
| Test location | /workspace/coverage/default/5.prim_esc_test.2679970355 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5336678 ps |
| CPU time | 0.36 seconds |
| Started | Apr 18 01:34:12 PM PDT 24 |
| Finished | Apr 18 01:34:14 PM PDT 24 |
| Peak memory | 146500 kb |
| Host | smart-938eac37-2824-4117-8c03-b11faa2f1d78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679970355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2679970355 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.599623065 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4923347 ps |
| CPU time | 0.42 seconds |
| Started | Apr 18 01:34:13 PM PDT 24 |
| Finished | Apr 18 01:34:14 PM PDT 24 |
| Peak memory | 146460 kb |
| Host | smart-0a6ac055-bae4-449b-9f86-935f0f7fa061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599623065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.599623065 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3047370118 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5034357 ps |
| CPU time | 0.4 seconds |
| Started | Apr 18 01:33:57 PM PDT 24 |
| Finished | Apr 18 01:33:58 PM PDT 24 |
| Peak memory | 146416 kb |
| Host | smart-d35f3c2d-cf76-481e-aec1-e92f6ff19a29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047370118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3047370118 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2984250373 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4595795 ps |
| CPU time | 0.36 seconds |
| Started | Apr 18 01:34:06 PM PDT 24 |
| Finished | Apr 18 01:34:07 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-d8e26fc1-b07f-4f52-b502-d54163f36e87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984250373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2984250373 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.24360997 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4332249 ps |
| CPU time | 0.39 seconds |
| Started | Apr 18 01:33:56 PM PDT 24 |
| Finished | Apr 18 01:33:58 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-41a9d93d-b5ae-4859-afd5-c9528d38933b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24360997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.24360997 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1999501987 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4541647 ps |
| CPU time | 0.4 seconds |
| Started | Apr 18 01:34:15 PM PDT 24 |
| Finished | Apr 18 01:34:16 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-45151388-1ace-40df-8c64-3abcb096344c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999501987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1999501987 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.946451445 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4852806 ps |
| CPU time | 0.4 seconds |
| Started | Apr 18 01:34:02 PM PDT 24 |
| Finished | Apr 18 01:34:02 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-b0069bca-2bae-4e04-a6dd-9c40122fa17b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946451445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.946451445 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1758201998 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4692031 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:34:02 PM PDT 24 |
| Finished | Apr 18 01:34:03 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-de6ad6b9-d1a6-4297-8154-47bc72570b94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758201998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1758201998 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3238163310 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5335911 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:34:07 PM PDT 24 |
| Finished | Apr 18 01:34:08 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-2c2d2317-f195-446f-9395-3005f713dbb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238163310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3238163310 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1859760025 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4259625 ps |
| CPU time | 0.37 seconds |
| Started | Apr 18 01:34:06 PM PDT 24 |
| Finished | Apr 18 01:34:07 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-3c892017-9e9b-472d-9cd8-9170093d73ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859760025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1859760025 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1276470103 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4643580 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:34:22 PM PDT 24 |
| Finished | Apr 18 01:34:24 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-67d5a939-2461-440b-b3ab-01f956feec0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276470103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1276470103 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3986711143 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4599215 ps |
| CPU time | 0.37 seconds |
| Started | Apr 18 01:34:06 PM PDT 24 |
| Finished | Apr 18 01:34:08 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-3127a511-1a84-44b1-af02-e383ca027954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986711143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3986711143 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1705293534 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4974440 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:34:00 PM PDT 24 |
| Finished | Apr 18 01:34:01 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-371ae1d9-aa07-45c8-afba-cd47585f761d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705293534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1705293534 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3409479192 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5046748 ps |
| CPU time | 0.39 seconds |
| Started | Apr 18 01:34:20 PM PDT 24 |
| Finished | Apr 18 01:34:21 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-fb620c1a-9264-43d2-934c-582ed676fab6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409479192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3409479192 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2569463075 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4404268 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:34:16 PM PDT 24 |
| Finished | Apr 18 01:34:16 PM PDT 24 |
| Peak memory | 146428 kb |
| Host | smart-99263a01-4a30-42cc-aaa0-ff561ea1a5e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569463075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2569463075 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2817360876 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5397822 ps |
| CPU time | 0.39 seconds |
| Started | Apr 18 01:34:35 PM PDT 24 |
| Finished | Apr 18 01:34:36 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-c8a77230-ecea-42ed-8a9b-4c31101a8645 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817360876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2817360876 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2335362985 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5112860 ps |
| CPU time | 0.37 seconds |
| Started | Apr 18 01:33:53 PM PDT 24 |
| Finished | Apr 18 01:33:54 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-af268050-dd80-49d9-9c3f-8db8944b27c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335362985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2335362985 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3422408266 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4631978 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:34:04 PM PDT 24 |
| Finished | Apr 18 01:34:05 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-cf8f2d96-cc60-4781-8615-976a6338531f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422408266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3422408266 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4218155831 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4664466 ps |
| CPU time | 0.4 seconds |
| Started | Apr 18 01:34:05 PM PDT 24 |
| Finished | Apr 18 01:34:06 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-14ba0309-a1a4-4ef2-b67a-1d0d43652f0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218155831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4218155831 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3357576714 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4894717 ps |
| CPU time | 0.38 seconds |
| Started | Apr 18 01:33:59 PM PDT 24 |
| Finished | Apr 18 01:33:59 PM PDT 24 |
| Peak memory | 146392 kb |
| Host | smart-bc18dc96-e8c4-462d-8c1a-efeb6646fc21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357576714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3357576714 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |