| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.56 | 85.56 | 92.38 | 92.38 | 79.55 | 79.55 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/4.prim_esc_test.2684197414 |
| 88.44 | 2.87 | 93.33 | 0.95 | 86.36 | 6.82 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3605191492 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.59235040 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/6.prim_esc_test.4257205015 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3188385963 |
| /workspace/coverage/default/1.prim_esc_test.555992591 |
| /workspace/coverage/default/10.prim_esc_test.3713735863 |
| /workspace/coverage/default/11.prim_esc_test.299972486 |
| /workspace/coverage/default/12.prim_esc_test.447118007 |
| /workspace/coverage/default/13.prim_esc_test.1689783514 |
| /workspace/coverage/default/14.prim_esc_test.1420322261 |
| /workspace/coverage/default/16.prim_esc_test.2151862840 |
| /workspace/coverage/default/17.prim_esc_test.362566416 |
| /workspace/coverage/default/18.prim_esc_test.4082840431 |
| /workspace/coverage/default/19.prim_esc_test.465632366 |
| /workspace/coverage/default/3.prim_esc_test.2080754732 |
| /workspace/coverage/default/5.prim_esc_test.2323766606 |
| /workspace/coverage/default/7.prim_esc_test.3204689772 |
| /workspace/coverage/default/8.prim_esc_test.2805831292 |
| /workspace/coverage/default/9.prim_esc_test.3706459857 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_esc_test.465632366 | Apr 21 12:41:38 PM PDT 24 | Apr 21 12:41:39 PM PDT 24 | 4725441 ps | ||
| T2 | /workspace/coverage/default/3.prim_esc_test.2080754732 | Apr 21 12:41:28 PM PDT 24 | Apr 21 12:41:29 PM PDT 24 | 4664645 ps | ||
| T3 | /workspace/coverage/default/11.prim_esc_test.299972486 | Apr 21 12:41:45 PM PDT 24 | Apr 21 12:41:46 PM PDT 24 | 4671282 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.1420322261 | Apr 21 12:41:29 PM PDT 24 | Apr 21 12:41:30 PM PDT 24 | 4654183 ps | ||
| T4 | /workspace/coverage/default/6.prim_esc_test.4257205015 | Apr 21 12:41:28 PM PDT 24 | Apr 21 12:41:29 PM PDT 24 | 4887603 ps | ||
| T8 | /workspace/coverage/default/5.prim_esc_test.2323766606 | Apr 21 12:41:52 PM PDT 24 | Apr 21 12:41:58 PM PDT 24 | 4634698 ps | ||
| T11 | /workspace/coverage/default/16.prim_esc_test.2151862840 | Apr 21 12:41:52 PM PDT 24 | Apr 21 12:41:53 PM PDT 24 | 5043304 ps | ||
| T14 | /workspace/coverage/default/8.prim_esc_test.2805831292 | Apr 21 12:41:44 PM PDT 24 | Apr 21 12:41:45 PM PDT 24 | 4516387 ps | ||
| T12 | /workspace/coverage/default/2.prim_esc_test.59235040 | Apr 21 12:41:26 PM PDT 24 | Apr 21 12:41:27 PM PDT 24 | 4538328 ps | ||
| T9 | /workspace/coverage/default/4.prim_esc_test.2684197414 | Apr 21 12:41:37 PM PDT 24 | Apr 21 12:41:37 PM PDT 24 | 4465854 ps | ||
| T10 | /workspace/coverage/default/9.prim_esc_test.3706459857 | Apr 21 12:41:47 PM PDT 24 | Apr 21 12:41:48 PM PDT 24 | 4417723 ps | ||
| T15 | /workspace/coverage/default/7.prim_esc_test.3204689772 | Apr 21 12:41:35 PM PDT 24 | Apr 21 12:41:36 PM PDT 24 | 4837046 ps | ||
| T16 | /workspace/coverage/default/18.prim_esc_test.4082840431 | Apr 21 12:41:39 PM PDT 24 | Apr 21 12:41:40 PM PDT 24 | 4357941 ps | ||
| T17 | /workspace/coverage/default/0.prim_esc_test.3188385963 | Apr 21 12:41:42 PM PDT 24 | Apr 21 12:41:42 PM PDT 24 | 5051975 ps | ||
| T18 | /workspace/coverage/default/12.prim_esc_test.447118007 | Apr 21 12:41:41 PM PDT 24 | Apr 21 12:41:42 PM PDT 24 | 4692797 ps | ||
| T6 | /workspace/coverage/default/15.prim_esc_test.3605191492 | Apr 21 12:41:46 PM PDT 24 | Apr 21 12:41:47 PM PDT 24 | 5003036 ps | ||
| T13 | /workspace/coverage/default/13.prim_esc_test.1689783514 | Apr 21 12:41:40 PM PDT 24 | Apr 21 12:41:41 PM PDT 24 | 4596675 ps | ||
| T7 | /workspace/coverage/default/10.prim_esc_test.3713735863 | Apr 21 12:41:32 PM PDT 24 | Apr 21 12:41:32 PM PDT 24 | 5061095 ps | ||
| T19 | /workspace/coverage/default/1.prim_esc_test.555992591 | Apr 21 12:41:35 PM PDT 24 | Apr 21 12:41:36 PM PDT 24 | 4524757 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.362566416 | Apr 21 12:41:49 PM PDT 24 | Apr 21 12:41:49 PM PDT 24 | 4840209 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.2684197414 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4465854 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:41:37 PM PDT 24 |
| Finished | Apr 21 12:41:37 PM PDT 24 |
| Peak memory | 146212 kb |
| Host | smart-311c0cab-489a-492e-b236-165a970f7eb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684197414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2684197414 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3605191492 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5003036 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:41:46 PM PDT 24 |
| Finished | Apr 21 12:41:47 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-37147beb-9e38-48a9-96f8-15963b9bf785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605191492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3605191492 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.59235040 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4538328 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:41:26 PM PDT 24 |
| Finished | Apr 21 12:41:27 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-c4b0b12c-b9b6-43d2-ab33-d9fb4a6a145d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59235040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.59235040 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4257205015 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4887603 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:41:28 PM PDT 24 |
| Finished | Apr 21 12:41:29 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-1ce6410b-c189-4138-be82-e87a709136fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257205015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4257205015 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3188385963 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5051975 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:41:42 PM PDT 24 |
| Finished | Apr 21 12:41:42 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-3044e5c8-5b67-42e4-883b-5389353169fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188385963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3188385963 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.555992591 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4524757 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:41:35 PM PDT 24 |
| Finished | Apr 21 12:41:36 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-4d1aac6a-2ec3-41de-a1fa-d89f0b2ffdbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555992591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.555992591 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3713735863 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5061095 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:41:32 PM PDT 24 |
| Finished | Apr 21 12:41:32 PM PDT 24 |
| Peak memory | 147888 kb |
| Host | smart-b0ca18d8-c36e-4e8d-a59d-f92b8854c061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713735863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3713735863 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.299972486 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4671282 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:41:45 PM PDT 24 |
| Finished | Apr 21 12:41:46 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-56e980a6-dbe5-4dc5-b7fe-3c3ca92d06cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299972486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.299972486 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.447118007 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4692797 ps |
| CPU time | 0.42 seconds |
| Started | Apr 21 12:41:41 PM PDT 24 |
| Finished | Apr 21 12:41:42 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-1800c8a7-80dc-436d-b5c6-aef49f165610 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447118007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.447118007 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1689783514 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4596675 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:41:40 PM PDT 24 |
| Finished | Apr 21 12:41:41 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-754a1050-09e7-4671-9212-8680b01fceb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689783514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1689783514 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1420322261 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4654183 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:41:29 PM PDT 24 |
| Finished | Apr 21 12:41:30 PM PDT 24 |
| Peak memory | 147820 kb |
| Host | smart-1b552153-396a-4397-9070-af6f6a0811f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420322261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1420322261 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2151862840 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5043304 ps |
| CPU time | 0.36 seconds |
| Started | Apr 21 12:41:52 PM PDT 24 |
| Finished | Apr 21 12:41:53 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-81108b1d-1931-4164-872d-1a4d06105d93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151862840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2151862840 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.362566416 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4840209 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:41:49 PM PDT 24 |
| Finished | Apr 21 12:41:49 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-dd05e889-5a80-4819-8097-4313ac21b5ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362566416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.362566416 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.4082840431 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4357941 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:41:39 PM PDT 24 |
| Finished | Apr 21 12:41:40 PM PDT 24 |
| Peak memory | 147824 kb |
| Host | smart-71d74d0e-0900-47cc-a063-c68824c461c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082840431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.4082840431 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.465632366 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4725441 ps |
| CPU time | 0.36 seconds |
| Started | Apr 21 12:41:38 PM PDT 24 |
| Finished | Apr 21 12:41:39 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-2c7dacf0-88dd-420a-8954-c3e334a85490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465632366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.465632366 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2080754732 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4664645 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:41:28 PM PDT 24 |
| Finished | Apr 21 12:41:29 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-b6062b9d-19bc-46ad-9390-315afe58e3b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080754732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2080754732 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2323766606 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4634698 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:41:52 PM PDT 24 |
| Finished | Apr 21 12:41:58 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-1f0845d4-adde-4d15-afa7-50c0423d9ef1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323766606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2323766606 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3204689772 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4837046 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:41:35 PM PDT 24 |
| Finished | Apr 21 12:41:36 PM PDT 24 |
| Peak memory | 146188 kb |
| Host | smart-f8f45f6a-f3ba-4c00-b760-efac9f648113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204689772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3204689772 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2805831292 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4516387 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:41:44 PM PDT 24 |
| Finished | Apr 21 12:41:45 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-bf404f67-480e-4c36-9167-9af61502aa63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805831292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2805831292 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3706459857 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4417723 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:41:47 PM PDT 24 |
| Finished | Apr 21 12:41:48 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-75c2b16f-b6fc-40e1-b7b2-ff44f63eabe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706459857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3706459857 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |