| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.1449108323 |
| 87.84 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.4240576010 |
| 89.58 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.337140364 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.72130279 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.802359129 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.208352962 |
| /workspace/coverage/default/12.prim_esc_test.3480770741 |
| /workspace/coverage/default/13.prim_esc_test.3139703152 |
| /workspace/coverage/default/15.prim_esc_test.1932916290 |
| /workspace/coverage/default/16.prim_esc_test.2463272396 |
| /workspace/coverage/default/18.prim_esc_test.498911824 |
| /workspace/coverage/default/19.prim_esc_test.1125838627 |
| /workspace/coverage/default/2.prim_esc_test.2238135856 |
| /workspace/coverage/default/3.prim_esc_test.498949671 |
| /workspace/coverage/default/4.prim_esc_test.1064491548 |
| /workspace/coverage/default/5.prim_esc_test.712473073 |
| /workspace/coverage/default/6.prim_esc_test.3302848140 |
| /workspace/coverage/default/7.prim_esc_test.432447149 |
| /workspace/coverage/default/8.prim_esc_test.174814835 |
| /workspace/coverage/default/9.prim_esc_test.1493176575 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_esc_test.498911824 | Apr 23 01:36:23 PM PDT 24 | Apr 23 01:36:24 PM PDT 24 | 4293877 ps | ||
| T2 | /workspace/coverage/default/3.prim_esc_test.498949671 | Apr 23 01:36:20 PM PDT 24 | Apr 23 01:36:21 PM PDT 24 | 5406830 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.4240576010 | Apr 23 01:36:24 PM PDT 24 | Apr 23 01:36:25 PM PDT 24 | 5207446 ps | ||
| T4 | /workspace/coverage/default/7.prim_esc_test.432447149 | Apr 23 01:36:21 PM PDT 24 | Apr 23 01:36:21 PM PDT 24 | 5248903 ps | ||
| T8 | /workspace/coverage/default/6.prim_esc_test.3302848140 | Apr 23 01:36:24 PM PDT 24 | Apr 23 01:36:26 PM PDT 24 | 4865609 ps | ||
| T16 | /workspace/coverage/default/9.prim_esc_test.1493176575 | Apr 23 01:36:21 PM PDT 24 | Apr 23 01:36:22 PM PDT 24 | 5140832 ps | ||
| T5 | /workspace/coverage/default/13.prim_esc_test.3139703152 | Apr 23 01:36:25 PM PDT 24 | Apr 23 01:36:27 PM PDT 24 | 4988889 ps | ||
| T13 | /workspace/coverage/default/12.prim_esc_test.3480770741 | Apr 23 01:36:20 PM PDT 24 | Apr 23 01:36:20 PM PDT 24 | 4616677 ps | ||
| T11 | /workspace/coverage/default/19.prim_esc_test.1125838627 | Apr 23 01:36:22 PM PDT 24 | Apr 23 01:36:23 PM PDT 24 | 3920375 ps | ||
| T6 | /workspace/coverage/default/1.prim_esc_test.1449108323 | Apr 23 01:36:19 PM PDT 24 | Apr 23 01:36:19 PM PDT 24 | 4752026 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.802359129 | Apr 23 01:36:23 PM PDT 24 | Apr 23 01:36:24 PM PDT 24 | 4774234 ps | ||
| T7 | /workspace/coverage/default/2.prim_esc_test.2238135856 | Apr 23 01:36:19 PM PDT 24 | Apr 23 01:36:19 PM PDT 24 | 4750860 ps | ||
| T17 | /workspace/coverage/default/16.prim_esc_test.2463272396 | Apr 23 01:36:24 PM PDT 24 | Apr 23 01:36:25 PM PDT 24 | 5213578 ps | ||
| T18 | /workspace/coverage/default/8.prim_esc_test.174814835 | Apr 23 01:36:26 PM PDT 24 | Apr 23 01:36:27 PM PDT 24 | 4525632 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.1064491548 | Apr 23 01:36:19 PM PDT 24 | Apr 23 01:36:20 PM PDT 24 | 5061714 ps | ||
| T10 | /workspace/coverage/default/14.prim_esc_test.72130279 | Apr 23 01:36:23 PM PDT 24 | Apr 23 01:36:24 PM PDT 24 | 5664574 ps | ||
| T9 | /workspace/coverage/default/0.prim_esc_test.208352962 | Apr 23 01:36:22 PM PDT 24 | Apr 23 01:36:23 PM PDT 24 | 4982092 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.337140364 | Apr 23 01:36:20 PM PDT 24 | Apr 23 01:36:20 PM PDT 24 | 5084092 ps | ||
| T20 | /workspace/coverage/default/15.prim_esc_test.1932916290 | Apr 23 01:36:21 PM PDT 24 | Apr 23 01:36:22 PM PDT 24 | 4836849 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.712473073 | Apr 23 01:36:19 PM PDT 24 | Apr 23 01:36:20 PM PDT 24 | 4802644 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.1449108323 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4752026 ps |
| CPU time | 0.39 seconds |
| Started | Apr 23 01:36:19 PM PDT 24 |
| Finished | Apr 23 01:36:19 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-ede0a26c-8b51-436f-9503-b28e3ebbb4dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449108323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1449108323 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.4240576010 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5207446 ps |
| CPU time | 0.39 seconds |
| Started | Apr 23 01:36:24 PM PDT 24 |
| Finished | Apr 23 01:36:25 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-04133be0-c441-4e15-8a52-f895376ebb11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240576010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4240576010 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.337140364 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5084092 ps |
| CPU time | 0.37 seconds |
| Started | Apr 23 01:36:20 PM PDT 24 |
| Finished | Apr 23 01:36:20 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-1330e963-1903-4445-a7b0-6e9bcd8c5e59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337140364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.337140364 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.72130279 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5664574 ps |
| CPU time | 0.39 seconds |
| Started | Apr 23 01:36:23 PM PDT 24 |
| Finished | Apr 23 01:36:24 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-9a4e1e8a-748c-4c3f-9a93-755b08edddd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72130279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.72130279 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.802359129 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4774234 ps |
| CPU time | 0.38 seconds |
| Started | Apr 23 01:36:23 PM PDT 24 |
| Finished | Apr 23 01:36:24 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-4048bbed-44d3-493f-af89-80d60d926b75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802359129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.802359129 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.208352962 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4982092 ps |
| CPU time | 0.44 seconds |
| Started | Apr 23 01:36:22 PM PDT 24 |
| Finished | Apr 23 01:36:23 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-5a160a6e-387f-45be-8831-891d59977c6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208352962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.208352962 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3480770741 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4616677 ps |
| CPU time | 0.38 seconds |
| Started | Apr 23 01:36:20 PM PDT 24 |
| Finished | Apr 23 01:36:20 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-7cb2cff8-57c7-4d66-8d6b-e1d2498dc0ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480770741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3480770741 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3139703152 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4988889 ps |
| CPU time | 0.38 seconds |
| Started | Apr 23 01:36:25 PM PDT 24 |
| Finished | Apr 23 01:36:27 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-6fcd9fec-8eab-4999-8308-ec61f78d5ed2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139703152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3139703152 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1932916290 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4836849 ps |
| CPU time | 0.4 seconds |
| Started | Apr 23 01:36:21 PM PDT 24 |
| Finished | Apr 23 01:36:22 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-abd80e0c-877c-4e2f-9e06-85de32218ac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932916290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1932916290 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2463272396 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5213578 ps |
| CPU time | 0.41 seconds |
| Started | Apr 23 01:36:24 PM PDT 24 |
| Finished | Apr 23 01:36:25 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-627c951d-b02a-4c35-a9ac-c1cd8e138ff3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463272396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2463272396 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.498911824 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4293877 ps |
| CPU time | 0.38 seconds |
| Started | Apr 23 01:36:23 PM PDT 24 |
| Finished | Apr 23 01:36:24 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-3b2741c9-75c5-4ae6-afc9-c362e5968502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498911824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.498911824 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1125838627 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3920375 ps |
| CPU time | 0.37 seconds |
| Started | Apr 23 01:36:22 PM PDT 24 |
| Finished | Apr 23 01:36:23 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-2b115fc6-e1d5-42f2-be16-824f24600549 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125838627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1125838627 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2238135856 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4750860 ps |
| CPU time | 0.38 seconds |
| Started | Apr 23 01:36:19 PM PDT 24 |
| Finished | Apr 23 01:36:19 PM PDT 24 |
| Peak memory | 146240 kb |
| Host | smart-2e8483b1-b74b-4a11-96d7-8ea4ca718d73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238135856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2238135856 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.498949671 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5406830 ps |
| CPU time | 0.38 seconds |
| Started | Apr 23 01:36:20 PM PDT 24 |
| Finished | Apr 23 01:36:21 PM PDT 24 |
| Peak memory | 146220 kb |
| Host | smart-39d382bd-e9ff-4003-9136-3419cbdffefa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498949671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.498949671 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1064491548 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5061714 ps |
| CPU time | 0.39 seconds |
| Started | Apr 23 01:36:19 PM PDT 24 |
| Finished | Apr 23 01:36:20 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-66f424e8-c6a2-4e73-bdd0-371b351df420 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064491548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1064491548 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.712473073 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4802644 ps |
| CPU time | 0.4 seconds |
| Started | Apr 23 01:36:19 PM PDT 24 |
| Finished | Apr 23 01:36:20 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-c93ae7bf-0ac1-44ab-8891-426cb6c6e849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712473073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.712473073 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3302848140 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4865609 ps |
| CPU time | 0.37 seconds |
| Started | Apr 23 01:36:24 PM PDT 24 |
| Finished | Apr 23 01:36:26 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-8864fa4d-c09b-4334-b636-2a190ce9ac1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302848140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3302848140 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.432447149 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5248903 ps |
| CPU time | 0.36 seconds |
| Started | Apr 23 01:36:21 PM PDT 24 |
| Finished | Apr 23 01:36:21 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-023bbba5-4f1c-46d3-96be-01c998616c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432447149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.432447149 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.174814835 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4525632 ps |
| CPU time | 0.39 seconds |
| Started | Apr 23 01:36:26 PM PDT 24 |
| Finished | Apr 23 01:36:27 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-17d4d993-ab6f-42b3-a711-0b823ba70553 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174814835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.174814835 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1493176575 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5140832 ps |
| CPU time | 0.39 seconds |
| Started | Apr 23 01:36:21 PM PDT 24 |
| Finished | Apr 23 01:36:22 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-93127c5f-edcb-492e-accc-d0f521c57484 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493176575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1493176575 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |