| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.40 | 85.40 | 90.48 | 90.48 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/17.prim_esc_test.316338408 |
| 88.44 | 3.04 | 93.33 | 2.86 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.3519248137 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.2567615203 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.3968045280 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1826407445 |
| /workspace/coverage/default/1.prim_esc_test.4060231476 |
| /workspace/coverage/default/11.prim_esc_test.2862459007 |
| /workspace/coverage/default/13.prim_esc_test.1112154537 |
| /workspace/coverage/default/14.prim_esc_test.4097640077 |
| /workspace/coverage/default/15.prim_esc_test.2814022400 |
| /workspace/coverage/default/16.prim_esc_test.2340551166 |
| /workspace/coverage/default/18.prim_esc_test.2977826371 |
| /workspace/coverage/default/19.prim_esc_test.2596301013 |
| /workspace/coverage/default/2.prim_esc_test.616705875 |
| /workspace/coverage/default/3.prim_esc_test.2337109581 |
| /workspace/coverage/default/5.prim_esc_test.1758213535 |
| /workspace/coverage/default/6.prim_esc_test.797160802 |
| /workspace/coverage/default/7.prim_esc_test.3206798213 |
| /workspace/coverage/default/8.prim_esc_test.1603621314 |
| /workspace/coverage/default/9.prim_esc_test.2975003554 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_esc_test.2340551166 | Apr 25 12:44:29 PM PDT 24 | Apr 25 12:44:31 PM PDT 24 | 5146922 ps | ||
| T2 | /workspace/coverage/default/13.prim_esc_test.1112154537 | Apr 25 12:44:18 PM PDT 24 | Apr 25 12:44:21 PM PDT 24 | 5025710 ps | ||
| T3 | /workspace/coverage/default/11.prim_esc_test.2862459007 | Apr 25 12:44:33 PM PDT 24 | Apr 25 12:44:34 PM PDT 24 | 4555557 ps | ||
| T7 | /workspace/coverage/default/19.prim_esc_test.2596301013 | Apr 25 12:44:22 PM PDT 24 | Apr 25 12:44:25 PM PDT 24 | 5305710 ps | ||
| T4 | /workspace/coverage/default/15.prim_esc_test.2814022400 | Apr 25 12:44:21 PM PDT 24 | Apr 25 12:44:25 PM PDT 24 | 4773527 ps | ||
| T5 | /workspace/coverage/default/3.prim_esc_test.2337109581 | Apr 25 12:44:23 PM PDT 24 | Apr 25 12:44:27 PM PDT 24 | 4874927 ps | ||
| T14 | /workspace/coverage/default/1.prim_esc_test.4060231476 | Apr 25 12:44:23 PM PDT 24 | Apr 25 12:44:27 PM PDT 24 | 4465264 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.3968045280 | Apr 25 12:44:23 PM PDT 24 | Apr 25 12:44:27 PM PDT 24 | 4995763 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.2567615203 | Apr 25 12:44:25 PM PDT 24 | Apr 25 12:44:28 PM PDT 24 | 4941659 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.316338408 | Apr 25 12:44:25 PM PDT 24 | Apr 25 12:44:28 PM PDT 24 | 5278470 ps | ||
| T15 | /workspace/coverage/default/18.prim_esc_test.2977826371 | Apr 25 12:44:31 PM PDT 24 | Apr 25 12:44:33 PM PDT 24 | 5166900 ps | ||
| T16 | /workspace/coverage/default/8.prim_esc_test.1603621314 | Apr 25 12:44:26 PM PDT 24 | Apr 25 12:44:30 PM PDT 24 | 5460118 ps | ||
| T17 | /workspace/coverage/default/9.prim_esc_test.2975003554 | Apr 25 12:44:33 PM PDT 24 | Apr 25 12:44:34 PM PDT 24 | 4990525 ps | ||
| T18 | /workspace/coverage/default/5.prim_esc_test.1758213535 | Apr 25 12:44:29 PM PDT 24 | Apr 25 12:44:31 PM PDT 24 | 5231618 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.3519248137 | Apr 25 12:44:25 PM PDT 24 | Apr 25 12:44:28 PM PDT 24 | 4486265 ps | ||
| T12 | /workspace/coverage/default/0.prim_esc_test.1826407445 | Apr 25 12:44:22 PM PDT 24 | Apr 25 12:44:25 PM PDT 24 | 4898857 ps | ||
| T13 | /workspace/coverage/default/7.prim_esc_test.3206798213 | Apr 25 12:44:26 PM PDT 24 | Apr 25 12:44:30 PM PDT 24 | 4737935 ps | ||
| T19 | /workspace/coverage/default/2.prim_esc_test.616705875 | Apr 25 12:44:26 PM PDT 24 | Apr 25 12:44:30 PM PDT 24 | 4831434 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.797160802 | Apr 25 12:44:33 PM PDT 24 | Apr 25 12:44:35 PM PDT 24 | 4861302 ps | ||
| T9 | /workspace/coverage/default/14.prim_esc_test.4097640077 | Apr 25 12:44:28 PM PDT 24 | Apr 25 12:44:31 PM PDT 24 | 5382884 ps |
| Test location | /workspace/coverage/default/17.prim_esc_test.316338408 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5278470 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:25 PM PDT 24 |
| Finished | Apr 25 12:44:28 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-6586b129-2bbe-459a-9836-1de59bdec4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316338408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.316338408 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3519248137 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4486265 ps |
| CPU time | 0.42 seconds |
| Started | Apr 25 12:44:25 PM PDT 24 |
| Finished | Apr 25 12:44:28 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-f129fe4d-1a78-4129-89b3-7d0ddb317327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519248137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3519248137 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2567615203 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4941659 ps |
| CPU time | 0.39 seconds |
| Started | Apr 25 12:44:25 PM PDT 24 |
| Finished | Apr 25 12:44:28 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-764ae32f-d336-4b9e-999c-e99638144637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567615203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2567615203 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3968045280 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4995763 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:23 PM PDT 24 |
| Finished | Apr 25 12:44:27 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-130ee1cf-b6de-4240-98fe-03b8607b18fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968045280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3968045280 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1826407445 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4898857 ps |
| CPU time | 0.37 seconds |
| Started | Apr 25 12:44:22 PM PDT 24 |
| Finished | Apr 25 12:44:25 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-9c966708-0f88-41b9-b3bd-64c93de4ddf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826407445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1826407445 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4060231476 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4465264 ps |
| CPU time | 0.37 seconds |
| Started | Apr 25 12:44:23 PM PDT 24 |
| Finished | Apr 25 12:44:27 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-b1d971f9-376f-4b6f-ae05-9c6235be6717 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060231476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4060231476 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2862459007 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4555557 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:33 PM PDT 24 |
| Finished | Apr 25 12:44:34 PM PDT 24 |
| Peak memory | 146448 kb |
| Host | smart-b655ff29-7e34-4edf-987c-62ad82a4afed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862459007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2862459007 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1112154537 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5025710 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:18 PM PDT 24 |
| Finished | Apr 25 12:44:21 PM PDT 24 |
| Peak memory | 146460 kb |
| Host | smart-2340f6fd-d396-469f-94c4-778ebeb5dbb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112154537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1112154537 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.4097640077 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5382884 ps |
| CPU time | 0.42 seconds |
| Started | Apr 25 12:44:28 PM PDT 24 |
| Finished | Apr 25 12:44:31 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-093f2b43-4b4e-4bd4-b5d1-5e502450f59a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097640077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4097640077 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2814022400 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4773527 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:21 PM PDT 24 |
| Finished | Apr 25 12:44:25 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-55be2420-af58-455a-bb2b-e98c1b0d4773 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814022400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2814022400 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2340551166 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5146922 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:29 PM PDT 24 |
| Finished | Apr 25 12:44:31 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-ddab7e03-62f7-4fe2-9c2b-03653d9c1305 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340551166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2340551166 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2977826371 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5166900 ps |
| CPU time | 0.41 seconds |
| Started | Apr 25 12:44:31 PM PDT 24 |
| Finished | Apr 25 12:44:33 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-8d1de148-7402-4d9d-b6d0-0c84bcd29eab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977826371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2977826371 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2596301013 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5305710 ps |
| CPU time | 0.37 seconds |
| Started | Apr 25 12:44:22 PM PDT 24 |
| Finished | Apr 25 12:44:25 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-9a920542-193a-4576-8b57-1c1b494e7bde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596301013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2596301013 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.616705875 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4831434 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:26 PM PDT 24 |
| Finished | Apr 25 12:44:30 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-425e7370-7962-406c-9359-b41344d95261 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616705875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.616705875 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2337109581 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4874927 ps |
| CPU time | 0.39 seconds |
| Started | Apr 25 12:44:23 PM PDT 24 |
| Finished | Apr 25 12:44:27 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-c7f6f839-670b-4843-bdbe-99bf39cfdf00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337109581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2337109581 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1758213535 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5231618 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:29 PM PDT 24 |
| Finished | Apr 25 12:44:31 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-f34296da-4dca-4a74-a9ca-c5550b1ba813 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758213535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1758213535 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.797160802 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4861302 ps |
| CPU time | 0.38 seconds |
| Started | Apr 25 12:44:33 PM PDT 24 |
| Finished | Apr 25 12:44:35 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-94e9f6b6-92c6-4a46-a174-90bbfd269943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797160802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.797160802 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3206798213 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4737935 ps |
| CPU time | 0.37 seconds |
| Started | Apr 25 12:44:26 PM PDT 24 |
| Finished | Apr 25 12:44:30 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-46fa8833-64dd-4544-929f-cf6972091d27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206798213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3206798213 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1603621314 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5460118 ps |
| CPU time | 0.37 seconds |
| Started | Apr 25 12:44:26 PM PDT 24 |
| Finished | Apr 25 12:44:30 PM PDT 24 |
| Peak memory | 146480 kb |
| Host | smart-c9908783-b8e8-4ce3-befb-43eb22052c11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603621314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1603621314 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2975003554 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4990525 ps |
| CPU time | 0.36 seconds |
| Started | Apr 25 12:44:33 PM PDT 24 |
| Finished | Apr 25 12:44:34 PM PDT 24 |
| Peak memory | 146460 kb |
| Host | smart-78e1ad25-3ef7-44c6-ad4c-e70ab526f3da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975003554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2975003554 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |