| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.3875366283 |
| 88.44 | 2.33 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2630443946 |
| 89.58 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.1433998103 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3325008791 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.4252356302 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.54044562 |
| /workspace/coverage/default/10.prim_esc_test.996798052 |
| /workspace/coverage/default/14.prim_esc_test.183565019 |
| /workspace/coverage/default/15.prim_esc_test.406003081 |
| /workspace/coverage/default/16.prim_esc_test.3431281168 |
| /workspace/coverage/default/17.prim_esc_test.2598799579 |
| /workspace/coverage/default/18.prim_esc_test.3840696579 |
| /workspace/coverage/default/19.prim_esc_test.560814437 |
| /workspace/coverage/default/2.prim_esc_test.375555923 |
| /workspace/coverage/default/3.prim_esc_test.2662024182 |
| /workspace/coverage/default/4.prim_esc_test.2405481842 |
| /workspace/coverage/default/5.prim_esc_test.3714892214 |
| /workspace/coverage/default/6.prim_esc_test.18992 |
| /workspace/coverage/default/7.prim_esc_test.1575274249 |
| /workspace/coverage/default/8.prim_esc_test.1860569499 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_esc_test.1433998103 | Apr 30 02:03:46 PM PDT 24 | Apr 30 02:03:47 PM PDT 24 | 4912924 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.1575274249 | Apr 30 02:03:46 PM PDT 24 | Apr 30 02:03:47 PM PDT 24 | 4703621 ps | ||
| T3 | /workspace/coverage/default/16.prim_esc_test.3431281168 | Apr 30 02:03:48 PM PDT 24 | Apr 30 02:03:49 PM PDT 24 | 4372011 ps | ||
| T7 | /workspace/coverage/default/5.prim_esc_test.3714892214 | Apr 30 02:03:45 PM PDT 24 | Apr 30 02:03:46 PM PDT 24 | 5174117 ps | ||
| T4 | /workspace/coverage/default/18.prim_esc_test.3840696579 | Apr 30 02:03:46 PM PDT 24 | Apr 30 02:03:47 PM PDT 24 | 4859243 ps | ||
| T5 | /workspace/coverage/default/15.prim_esc_test.406003081 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4901170 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.2405481842 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4520817 ps | ||
| T15 | /workspace/coverage/default/10.prim_esc_test.996798052 | Apr 30 02:03:49 PM PDT 24 | Apr 30 02:03:49 PM PDT 24 | 4872154 ps | ||
| T10 | /workspace/coverage/default/8.prim_esc_test.1860569499 | Apr 30 02:03:48 PM PDT 24 | Apr 30 02:03:49 PM PDT 24 | 4577619 ps | ||
| T8 | /workspace/coverage/default/12.prim_esc_test.3875366283 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4974215 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.2598799579 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 5175588 ps | ||
| T16 | /workspace/coverage/default/3.prim_esc_test.2662024182 | Apr 30 02:03:46 PM PDT 24 | Apr 30 02:03:46 PM PDT 24 | 4570179 ps | ||
| T13 | /workspace/coverage/default/19.prim_esc_test.560814437 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4480325 ps | ||
| T17 | /workspace/coverage/default/2.prim_esc_test.375555923 | Apr 30 02:03:49 PM PDT 24 | Apr 30 02:03:50 PM PDT 24 | 4779167 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.2630443946 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4955455 ps | ||
| T18 | /workspace/coverage/default/14.prim_esc_test.183565019 | Apr 30 02:03:46 PM PDT 24 | Apr 30 02:03:46 PM PDT 24 | 5053726 ps | ||
| T9 | /workspace/coverage/default/9.prim_esc_test.4252356302 | Apr 30 02:03:50 PM PDT 24 | Apr 30 02:03:51 PM PDT 24 | 5069074 ps | ||
| T19 | /workspace/coverage/default/6.prim_esc_test.18992 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4239174 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.3325008791 | Apr 30 02:03:48 PM PDT 24 | Apr 30 02:03:49 PM PDT 24 | 5240999 ps | ||
| T20 | /workspace/coverage/default/1.prim_esc_test.54044562 | Apr 30 02:03:47 PM PDT 24 | Apr 30 02:03:48 PM PDT 24 | 4646874 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.3875366283 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4974215 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146484 kb |
| Host | smart-9f01af9f-073d-4e8f-b0fd-3a4da847d4b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875366283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3875366283 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2630443946 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4955455 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-1e551d7d-e9d1-4da3-9166-8a8d2a66c5c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630443946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2630443946 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1433998103 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4912924 ps |
| CPU time | 0.36 seconds |
| Started | Apr 30 02:03:46 PM PDT 24 |
| Finished | Apr 30 02:03:47 PM PDT 24 |
| Peak memory | 146492 kb |
| Host | smart-2b7c1fe0-eda7-4385-9917-57cd6db1662b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433998103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1433998103 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3325008791 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5240999 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 02:03:48 PM PDT 24 |
| Finished | Apr 30 02:03:49 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-0891fb0b-d03c-418c-a7fb-aff7541eee77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325008791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3325008791 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.4252356302 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5069074 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 02:03:50 PM PDT 24 |
| Finished | Apr 30 02:03:51 PM PDT 24 |
| Peak memory | 146428 kb |
| Host | smart-7d7e6dda-063e-4124-802e-f5ddaa701f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252356302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4252356302 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.54044562 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4646874 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146408 kb |
| Host | smart-98f8a08f-4cb8-49e9-98d6-9365834ce6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54044562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.54044562 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.996798052 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4872154 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:49 PM PDT 24 |
| Finished | Apr 30 02:03:49 PM PDT 24 |
| Peak memory | 146424 kb |
| Host | smart-8c6c6e05-2f7a-440e-9dfe-a1fcc9f51f41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996798052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.996798052 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.183565019 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5053726 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:46 PM PDT 24 |
| Finished | Apr 30 02:03:46 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-edd757c4-4bd7-43db-8c54-88adc2a4e8cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183565019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.183565019 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.406003081 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4901170 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-0cbc1b4c-9643-45a1-80b9-5965c9d65bb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406003081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.406003081 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3431281168 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4372011 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:48 PM PDT 24 |
| Finished | Apr 30 02:03:49 PM PDT 24 |
| Peak memory | 146488 kb |
| Host | smart-aad2e024-42ff-46d5-a87f-db695772a9f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431281168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3431281168 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2598799579 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5175588 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146416 kb |
| Host | smart-8ee10dd0-9927-4248-b62c-a4af74e00234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598799579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2598799579 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3840696579 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4859243 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 02:03:46 PM PDT 24 |
| Finished | Apr 30 02:03:47 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-77eb7478-13fd-4435-ace1-38eb31722b31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840696579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3840696579 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.560814437 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4480325 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-a92740c0-6b46-4d0e-87da-cbe69631e8e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560814437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.560814437 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.375555923 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4779167 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:49 PM PDT 24 |
| Finished | Apr 30 02:03:50 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-3c417eae-2704-4bd8-83a0-32953bab4010 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375555923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.375555923 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2662024182 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4570179 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:46 PM PDT 24 |
| Finished | Apr 30 02:03:46 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-62a04454-fec0-49be-b406-93fe8e92a72a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662024182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2662024182 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2405481842 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4520817 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-7815e6b6-d5c5-4d5a-a0eb-2f68680ef003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405481842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2405481842 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3714892214 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5174117 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:45 PM PDT 24 |
| Finished | Apr 30 02:03:46 PM PDT 24 |
| Peak memory | 146448 kb |
| Host | smart-0d564449-9539-471f-a551-df94466ab246 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714892214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3714892214 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.18992 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4239174 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:47 PM PDT 24 |
| Finished | Apr 30 02:03:48 PM PDT 24 |
| Peak memory | 146448 kb |
| Host | smart-7e877c47-ec0c-4b65-b18e-8ad8c20928a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.18992 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1575274249 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4703621 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 02:03:46 PM PDT 24 |
| Finished | Apr 30 02:03:47 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-7f03f460-8c1b-4da1-b789-3baf7804649d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575274249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1575274249 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1860569499 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4577619 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 02:03:48 PM PDT 24 |
| Finished | Apr 30 02:03:49 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-5e59fdc7-a578-461a-b0f2-1da45c43aecc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860569499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1860569499 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |