| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.32 | 86.32 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/4.prim_esc_test.613638483 |
| 88.44 | 2.12 | 93.33 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.1586615964 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.2986700637 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.3946880516 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.947190397 |
| /workspace/coverage/default/1.prim_esc_test.3615276352 |
| /workspace/coverage/default/11.prim_esc_test.3831695945 |
| /workspace/coverage/default/13.prim_esc_test.450885585 |
| /workspace/coverage/default/14.prim_esc_test.1896993173 |
| /workspace/coverage/default/15.prim_esc_test.2016162669 |
| /workspace/coverage/default/16.prim_esc_test.2295732217 |
| /workspace/coverage/default/17.prim_esc_test.182573278 |
| /workspace/coverage/default/19.prim_esc_test.2402302570 |
| /workspace/coverage/default/2.prim_esc_test.854554187 |
| /workspace/coverage/default/3.prim_esc_test.625828790 |
| /workspace/coverage/default/5.prim_esc_test.3529138940 |
| /workspace/coverage/default/6.prim_esc_test.2725638253 |
| /workspace/coverage/default/7.prim_esc_test.170546570 |
| /workspace/coverage/default/8.prim_esc_test.970398976 |
| /workspace/coverage/default/9.prim_esc_test.1946784790 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_esc_test.182573278 | May 02 12:39:19 PM PDT 24 | May 02 12:39:21 PM PDT 24 | 5266946 ps | ||
| T2 | /workspace/coverage/default/9.prim_esc_test.1946784790 | May 02 12:39:17 PM PDT 24 | May 02 12:39:18 PM PDT 24 | 5146869 ps | ||
| T3 | /workspace/coverage/default/12.prim_esc_test.1586615964 | May 02 12:39:17 PM PDT 24 | May 02 12:39:19 PM PDT 24 | 4991061 ps | ||
| T4 | /workspace/coverage/default/3.prim_esc_test.625828790 | May 02 12:39:08 PM PDT 24 | May 02 12:39:09 PM PDT 24 | 4503577 ps | ||
| T6 | /workspace/coverage/default/6.prim_esc_test.2725638253 | May 02 12:39:19 PM PDT 24 | May 02 12:39:20 PM PDT 24 | 4956051 ps | ||
| T5 | /workspace/coverage/default/15.prim_esc_test.2016162669 | May 02 12:39:09 PM PDT 24 | May 02 12:39:10 PM PDT 24 | 4973088 ps | ||
| T11 | /workspace/coverage/default/18.prim_esc_test.2986700637 | May 02 12:39:16 PM PDT 24 | May 02 12:39:17 PM PDT 24 | 5197900 ps | ||
| T10 | /workspace/coverage/default/4.prim_esc_test.613638483 | May 02 12:39:18 PM PDT 24 | May 02 12:39:19 PM PDT 24 | 5036731 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.3615276352 | May 02 12:38:52 PM PDT 24 | May 02 12:38:55 PM PDT 24 | 4671460 ps | ||
| T14 | /workspace/coverage/default/19.prim_esc_test.2402302570 | May 02 12:39:32 PM PDT 24 | May 02 12:39:33 PM PDT 24 | 5104283 ps | ||
| T7 | /workspace/coverage/default/5.prim_esc_test.3529138940 | May 02 12:39:13 PM PDT 24 | May 02 12:39:15 PM PDT 24 | 4943075 ps | ||
| T15 | /workspace/coverage/default/14.prim_esc_test.1896993173 | May 02 12:39:44 PM PDT 24 | May 02 12:39:45 PM PDT 24 | 4970715 ps | ||
| T16 | /workspace/coverage/default/11.prim_esc_test.3831695945 | May 02 12:39:13 PM PDT 24 | May 02 12:39:15 PM PDT 24 | 4512492 ps | ||
| T13 | /workspace/coverage/default/7.prim_esc_test.170546570 | May 02 12:39:15 PM PDT 24 | May 02 12:39:16 PM PDT 24 | 4468662 ps | ||
| T17 | /workspace/coverage/default/0.prim_esc_test.947190397 | May 02 12:39:20 PM PDT 24 | May 02 12:39:21 PM PDT 24 | 5260282 ps | ||
| T8 | /workspace/coverage/default/8.prim_esc_test.970398976 | May 02 12:39:22 PM PDT 24 | May 02 12:39:23 PM PDT 24 | 4873772 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.2295732217 | May 02 12:39:25 PM PDT 24 | May 02 12:39:26 PM PDT 24 | 4520935 ps | ||
| T19 | /workspace/coverage/default/13.prim_esc_test.450885585 | May 02 12:39:26 PM PDT 24 | May 02 12:39:32 PM PDT 24 | 4311048 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.854554187 | May 02 12:39:26 PM PDT 24 | May 02 12:39:27 PM PDT 24 | 4630097 ps | ||
| T9 | /workspace/coverage/default/10.prim_esc_test.3946880516 | May 02 12:39:24 PM PDT 24 | May 02 12:39:25 PM PDT 24 | 4989716 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.613638483 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5036731 ps |
| CPU time | 0.37 seconds |
| Started | May 02 12:39:18 PM PDT 24 |
| Finished | May 02 12:39:19 PM PDT 24 |
| Peak memory | 146148 kb |
| Host | smart-a65c8101-4182-41b7-82f0-d0ac8f0e2b07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613638483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.613638483 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1586615964 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4991061 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:17 PM PDT 24 |
| Finished | May 02 12:39:19 PM PDT 24 |
| Peak memory | 146168 kb |
| Host | smart-c7c90325-af64-4843-a624-ab05c250be63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586615964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1586615964 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2986700637 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5197900 ps |
| CPU time | 0.37 seconds |
| Started | May 02 12:39:16 PM PDT 24 |
| Finished | May 02 12:39:17 PM PDT 24 |
| Peak memory | 146104 kb |
| Host | smart-a85c2633-31b9-4afb-8a60-6bf4a85307cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986700637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2986700637 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3946880516 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4989716 ps |
| CPU time | 0.36 seconds |
| Started | May 02 12:39:24 PM PDT 24 |
| Finished | May 02 12:39:25 PM PDT 24 |
| Peak memory | 146044 kb |
| Host | smart-218482dc-07db-47fa-b1b5-57fc21e0a88e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946880516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3946880516 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.947190397 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5260282 ps |
| CPU time | 0.37 seconds |
| Started | May 02 12:39:20 PM PDT 24 |
| Finished | May 02 12:39:21 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-316de9c6-4360-41b3-bcd9-a74a184e1fd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947190397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.947190397 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3615276352 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4671460 ps |
| CPU time | 0.37 seconds |
| Started | May 02 12:38:52 PM PDT 24 |
| Finished | May 02 12:38:55 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-701d9e0e-fc5d-44cc-b77e-1b34161ebbf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615276352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3615276352 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3831695945 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4512492 ps |
| CPU time | 0.41 seconds |
| Started | May 02 12:39:13 PM PDT 24 |
| Finished | May 02 12:39:15 PM PDT 24 |
| Peak memory | 146052 kb |
| Host | smart-8fc85282-aeba-4847-8ff4-1e61b63317e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831695945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3831695945 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.450885585 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4311048 ps |
| CPU time | 0.4 seconds |
| Started | May 02 12:39:26 PM PDT 24 |
| Finished | May 02 12:39:32 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-a5ef3a3b-be84-48b2-9736-a4cb1b8da71a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450885585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.450885585 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1896993173 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4970715 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:44 PM PDT 24 |
| Finished | May 02 12:39:45 PM PDT 24 |
| Peak memory | 146120 kb |
| Host | smart-e2109d95-7886-491c-8f75-a392ff567306 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896993173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1896993173 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2016162669 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4973088 ps |
| CPU time | 0.4 seconds |
| Started | May 02 12:39:09 PM PDT 24 |
| Finished | May 02 12:39:10 PM PDT 24 |
| Peak memory | 146148 kb |
| Host | smart-49e574e9-05ab-4c0b-9c94-8ba631360034 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016162669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2016162669 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2295732217 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4520935 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:25 PM PDT 24 |
| Finished | May 02 12:39:26 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-26016d92-c71d-423e-88ba-c63b6f7c8e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295732217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2295732217 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.182573278 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5266946 ps |
| CPU time | 0.36 seconds |
| Started | May 02 12:39:19 PM PDT 24 |
| Finished | May 02 12:39:21 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-0afe2340-0312-4f3c-abc8-614b8a3b5942 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182573278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.182573278 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2402302570 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5104283 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:32 PM PDT 24 |
| Finished | May 02 12:39:33 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-fb1845d4-4969-46b2-a7ab-66fe9f57aa4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402302570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2402302570 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.854554187 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4630097 ps |
| CPU time | 0.39 seconds |
| Started | May 02 12:39:26 PM PDT 24 |
| Finished | May 02 12:39:27 PM PDT 24 |
| Peak memory | 146120 kb |
| Host | smart-7655068a-85d7-46e6-8d27-14af9c5db476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854554187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.854554187 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.625828790 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4503577 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:08 PM PDT 24 |
| Finished | May 02 12:39:09 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-319deef7-f48e-4060-aa5c-50c6cf3725c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625828790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.625828790 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3529138940 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4943075 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:13 PM PDT 24 |
| Finished | May 02 12:39:15 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-f486a0d6-ee7d-43ee-98c6-117c38efb92f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529138940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3529138940 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2725638253 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4956051 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:19 PM PDT 24 |
| Finished | May 02 12:39:20 PM PDT 24 |
| Peak memory | 146024 kb |
| Host | smart-566de289-b9a2-4a5c-bb07-f44bd0c2df81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725638253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2725638253 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.170546570 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4468662 ps |
| CPU time | 0.4 seconds |
| Started | May 02 12:39:15 PM PDT 24 |
| Finished | May 02 12:39:16 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-43e03754-2fe5-494d-8d6f-8cf41ea00a9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170546570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.170546570 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.970398976 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4873772 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:22 PM PDT 24 |
| Finished | May 02 12:39:23 PM PDT 24 |
| Peak memory | 145948 kb |
| Host | smart-b9dac407-c1c9-416d-ad59-49106f9e8784 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970398976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.970398976 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1946784790 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5146869 ps |
| CPU time | 0.38 seconds |
| Started | May 02 12:39:17 PM PDT 24 |
| Finished | May 02 12:39:18 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-239b193f-1f4f-4369-816c-503c35c5f9d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946784790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1946784790 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |