| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.70 | 86.70 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/16.prim_esc_test.723388874 |
| 87.84 | 1.14 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 82.14 | 3.57 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2547505628 |
| 88.98 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2901278896 |
| 90.12 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.1453204144 |
| 90.72 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.415238759 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.504251340 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.399820417 |
| /workspace/coverage/default/12.prim_esc_test.2300614189 |
| /workspace/coverage/default/13.prim_esc_test.106657022 |
| /workspace/coverage/default/14.prim_esc_test.205075547 |
| /workspace/coverage/default/17.prim_esc_test.96096062 |
| /workspace/coverage/default/18.prim_esc_test.2134112789 |
| /workspace/coverage/default/19.prim_esc_test.24045525 |
| /workspace/coverage/default/3.prim_esc_test.3278974083 |
| /workspace/coverage/default/4.prim_esc_test.3666489503 |
| /workspace/coverage/default/5.prim_esc_test.2956409131 |
| /workspace/coverage/default/6.prim_esc_test.3569564831 |
| /workspace/coverage/default/7.prim_esc_test.4224848827 |
| /workspace/coverage/default/8.prim_esc_test.1647465459 |
| /workspace/coverage/default/9.prim_esc_test.2152790758 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_esc_test.205075547 | May 05 01:05:19 PM PDT 24 | May 05 01:05:20 PM PDT 24 | 5268302 ps | ||
| T2 | /workspace/coverage/default/4.prim_esc_test.3666489503 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 4774157 ps | ||
| T3 | /workspace/coverage/default/12.prim_esc_test.2300614189 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 4881249 ps | ||
| T6 | /workspace/coverage/default/8.prim_esc_test.1647465459 | May 05 01:05:19 PM PDT 24 | May 05 01:05:20 PM PDT 24 | 4997433 ps | ||
| T5 | /workspace/coverage/default/5.prim_esc_test.2956409131 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 4574827 ps | ||
| T4 | /workspace/coverage/default/16.prim_esc_test.723388874 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 5106865 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.1453204144 | May 05 01:05:20 PM PDT 24 | May 05 01:05:21 PM PDT 24 | 4781487 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.415238759 | May 05 01:05:17 PM PDT 24 | May 05 01:05:18 PM PDT 24 | 4919267 ps | ||
| T12 | /workspace/coverage/default/10.prim_esc_test.2547505628 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 5113788 ps | ||
| T10 | /workspace/coverage/default/2.prim_esc_test.504251340 | May 05 01:05:23 PM PDT 24 | May 05 01:05:24 PM PDT 24 | 4870649 ps | ||
| T11 | /workspace/coverage/default/1.prim_esc_test.399820417 | May 05 01:05:19 PM PDT 24 | May 05 01:05:20 PM PDT 24 | 4725272 ps | ||
| T16 | /workspace/coverage/default/7.prim_esc_test.4224848827 | May 05 01:05:19 PM PDT 24 | May 05 01:05:20 PM PDT 24 | 4727524 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.2901278896 | May 05 01:05:17 PM PDT 24 | May 05 01:05:18 PM PDT 24 | 5193193 ps | ||
| T17 | /workspace/coverage/default/13.prim_esc_test.106657022 | May 05 01:05:19 PM PDT 24 | May 05 01:05:20 PM PDT 24 | 5089293 ps | ||
| T18 | /workspace/coverage/default/17.prim_esc_test.96096062 | May 05 01:05:20 PM PDT 24 | May 05 01:05:21 PM PDT 24 | 4939433 ps | ||
| T8 | /workspace/coverage/default/9.prim_esc_test.2152790758 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 4600688 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.2134112789 | May 05 01:05:19 PM PDT 24 | May 05 01:05:20 PM PDT 24 | 4647288 ps | ||
| T20 | /workspace/coverage/default/3.prim_esc_test.3278974083 | May 05 01:05:17 PM PDT 24 | May 05 01:05:18 PM PDT 24 | 4915784 ps | ||
| T9 | /workspace/coverage/default/6.prim_esc_test.3569564831 | May 05 01:05:24 PM PDT 24 | May 05 01:05:24 PM PDT 24 | 4797166 ps | ||
| T14 | /workspace/coverage/default/19.prim_esc_test.24045525 | May 05 01:05:18 PM PDT 24 | May 05 01:05:19 PM PDT 24 | 4872191 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.723388874 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5106865 ps |
| CPU time | 0.38 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-46da7d43-fbcd-4f12-8287-694f589a515e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723388874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.723388874 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2547505628 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5113788 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-f039ef49-03c1-41d9-97aa-14e4d065224b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547505628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2547505628 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2901278896 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5193193 ps |
| CPU time | 0.38 seconds |
| Started | May 05 01:05:17 PM PDT 24 |
| Finished | May 05 01:05:18 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-c2902b35-08e6-4e64-b995-71da7fdcead2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901278896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2901278896 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1453204144 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4781487 ps |
| CPU time | 0.39 seconds |
| Started | May 05 01:05:20 PM PDT 24 |
| Finished | May 05 01:05:21 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-70c43876-7d94-407d-97e9-c3c67eccb265 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453204144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1453204144 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.415238759 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4919267 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:17 PM PDT 24 |
| Finished | May 05 01:05:18 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-270cc6d8-fc0f-4cd7-abbb-0e199bca3225 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415238759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.415238759 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.504251340 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4870649 ps |
| CPU time | 0.36 seconds |
| Started | May 05 01:05:23 PM PDT 24 |
| Finished | May 05 01:05:24 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-095edb62-c51e-4ba9-81a1-874a4db07bba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504251340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.504251340 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.399820417 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4725272 ps |
| CPU time | 0.4 seconds |
| Started | May 05 01:05:19 PM PDT 24 |
| Finished | May 05 01:05:20 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-4c399145-d655-4a9b-af6e-12d3760efeba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399820417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.399820417 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2300614189 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4881249 ps |
| CPU time | 0.38 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146556 kb |
| Host | smart-ae2f40a7-b380-47ca-9fbb-eb3e61f2dd76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300614189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2300614189 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.106657022 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5089293 ps |
| CPU time | 0.4 seconds |
| Started | May 05 01:05:19 PM PDT 24 |
| Finished | May 05 01:05:20 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-face3a9a-df54-4e42-9d3a-be0cbb409df4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106657022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.106657022 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.205075547 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5268302 ps |
| CPU time | 0.38 seconds |
| Started | May 05 01:05:19 PM PDT 24 |
| Finished | May 05 01:05:20 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-5a8a9655-cb93-4f7f-8e58-5f9e2f11f6d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205075547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.205075547 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.96096062 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4939433 ps |
| CPU time | 0.39 seconds |
| Started | May 05 01:05:20 PM PDT 24 |
| Finished | May 05 01:05:21 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-1d09df94-ed5d-44da-a3c6-25111ee7a63d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96096062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.96096062 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2134112789 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4647288 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:19 PM PDT 24 |
| Finished | May 05 01:05:20 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-514b048b-2fa8-4d39-88f6-7f6e02d9c5e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134112789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2134112789 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.24045525 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4872191 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-9995efc0-c678-4208-b5ad-349edae0929e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24045525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.24045525 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3278974083 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4915784 ps |
| CPU time | 0.41 seconds |
| Started | May 05 01:05:17 PM PDT 24 |
| Finished | May 05 01:05:18 PM PDT 24 |
| Peak memory | 146428 kb |
| Host | smart-324131fb-f028-4d4d-9e2f-4e7e10bd90a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278974083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3278974083 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3666489503 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4774157 ps |
| CPU time | 0.41 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-54fb28f2-07e0-457a-9712-18c056eb105e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666489503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3666489503 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2956409131 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4574827 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-31bd8a5c-5340-47a0-abd3-c9a6e14c033c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956409131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2956409131 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3569564831 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4797166 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:24 PM PDT 24 |
| Finished | May 05 01:05:24 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-14223013-1e02-4251-8414-36be33b21f76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569564831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3569564831 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4224848827 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4727524 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:19 PM PDT 24 |
| Finished | May 05 01:05:20 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-6a022c42-9889-4115-acb0-b75ee239a73b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224848827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4224848827 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1647465459 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4997433 ps |
| CPU time | 0.36 seconds |
| Started | May 05 01:05:19 PM PDT 24 |
| Finished | May 05 01:05:20 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-a4040b57-880d-4316-ad93-c390c0944a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647465459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1647465459 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2152790758 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4600688 ps |
| CPU time | 0.37 seconds |
| Started | May 05 01:05:18 PM PDT 24 |
| Finished | May 05 01:05:19 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-201263a2-3468-49e4-927d-a09bffea0ed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152790758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2152790758 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |