| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.72 | 85.72 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/2.prim_esc_test.3968521328 |
| 88.06 | 2.33 | 93.33 | 0.95 | 84.09 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.2939500653 |
| 90.17 | 2.12 | 94.29 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.2848128606 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.622077814 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.4160403995 |
| /workspace/coverage/default/10.prim_esc_test.1566630981 |
| /workspace/coverage/default/11.prim_esc_test.2142342142 |
| /workspace/coverage/default/12.prim_esc_test.434954394 |
| /workspace/coverage/default/13.prim_esc_test.4213409807 |
| /workspace/coverage/default/14.prim_esc_test.4017495094 |
| /workspace/coverage/default/15.prim_esc_test.238245831 |
| /workspace/coverage/default/16.prim_esc_test.1399100327 |
| /workspace/coverage/default/17.prim_esc_test.538818373 |
| /workspace/coverage/default/18.prim_esc_test.2779743478 |
| /workspace/coverage/default/3.prim_esc_test.1954790105 |
| /workspace/coverage/default/5.prim_esc_test.2391838531 |
| /workspace/coverage/default/6.prim_esc_test.234012953 |
| /workspace/coverage/default/7.prim_esc_test.4195006551 |
| /workspace/coverage/default/8.prim_esc_test.3371768515 |
| /workspace/coverage/default/9.prim_esc_test.2883037898 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_esc_test.234012953 | May 07 02:16:15 PM PDT 24 | May 07 02:16:16 PM PDT 24 | 4891306 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.4195006551 | May 07 02:16:15 PM PDT 24 | May 07 02:16:16 PM PDT 24 | 5027929 ps | ||
| T3 | /workspace/coverage/default/16.prim_esc_test.1399100327 | May 07 02:16:24 PM PDT 24 | May 07 02:16:25 PM PDT 24 | 4756909 ps | ||
| T8 | /workspace/coverage/default/2.prim_esc_test.3968521328 | May 07 02:16:13 PM PDT 24 | May 07 02:16:14 PM PDT 24 | 4596688 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.2939500653 | May 07 02:16:13 PM PDT 24 | May 07 02:16:14 PM PDT 24 | 4873130 ps | ||
| T4 | /workspace/coverage/default/14.prim_esc_test.4017495094 | May 07 02:16:24 PM PDT 24 | May 07 02:16:25 PM PDT 24 | 4787077 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.2391838531 | May 07 02:16:14 PM PDT 24 | May 07 02:16:15 PM PDT 24 | 5009973 ps | ||
| T5 | /workspace/coverage/default/1.prim_esc_test.622077814 | May 07 02:16:09 PM PDT 24 | May 07 02:16:10 PM PDT 24 | 5107941 ps | ||
| T10 | /workspace/coverage/default/18.prim_esc_test.2779743478 | May 07 02:16:31 PM PDT 24 | May 07 02:16:32 PM PDT 24 | 4903642 ps | ||
| T12 | /workspace/coverage/default/19.prim_esc_test.2848128606 | May 07 02:16:32 PM PDT 24 | May 07 02:16:32 PM PDT 24 | 4786024 ps | ||
| T13 | /workspace/coverage/default/9.prim_esc_test.2883037898 | May 07 02:16:19 PM PDT 24 | May 07 02:16:20 PM PDT 24 | 4714775 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.4213409807 | May 07 02:16:20 PM PDT 24 | May 07 02:16:21 PM PDT 24 | 4525619 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.434954394 | May 07 02:16:21 PM PDT 24 | May 07 02:16:22 PM PDT 24 | 4573722 ps | ||
| T17 | /workspace/coverage/default/15.prim_esc_test.238245831 | May 07 02:16:25 PM PDT 24 | May 07 02:16:26 PM PDT 24 | 4523399 ps | ||
| T9 | /workspace/coverage/default/17.prim_esc_test.538818373 | May 07 02:16:25 PM PDT 24 | May 07 02:16:26 PM PDT 24 | 5274027 ps | ||
| T14 | /workspace/coverage/default/3.prim_esc_test.1954790105 | May 07 02:16:12 PM PDT 24 | May 07 02:16:13 PM PDT 24 | 5272643 ps | ||
| T18 | /workspace/coverage/default/8.prim_esc_test.3371768515 | May 07 02:16:14 PM PDT 24 | May 07 02:16:15 PM PDT 24 | 4694232 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.2142342142 | May 07 02:16:20 PM PDT 24 | May 07 02:16:21 PM PDT 24 | 4887062 ps | ||
| T19 | /workspace/coverage/default/0.prim_esc_test.4160403995 | May 07 02:16:02 PM PDT 24 | May 07 02:16:03 PM PDT 24 | 4686961 ps | ||
| T20 | /workspace/coverage/default/10.prim_esc_test.1566630981 | May 07 02:16:23 PM PDT 24 | May 07 02:16:24 PM PDT 24 | 4671903 ps |
| Test location | /workspace/coverage/default/2.prim_esc_test.3968521328 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4596688 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:13 PM PDT 24 |
| Finished | May 07 02:16:14 PM PDT 24 |
| Peak memory | 146416 kb |
| Host | smart-1830057f-692b-4876-89e6-5908da78d59c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968521328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3968521328 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2939500653 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4873130 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:13 PM PDT 24 |
| Finished | May 07 02:16:14 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-52266da9-d49f-47f7-9045-ba63c102394a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939500653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2939500653 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2848128606 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4786024 ps |
| CPU time | 0.36 seconds |
| Started | May 07 02:16:32 PM PDT 24 |
| Finished | May 07 02:16:32 PM PDT 24 |
| Peak memory | 146524 kb |
| Host | smart-05e7f84d-65e9-46c3-976e-5e0e8c38fe27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848128606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2848128606 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.622077814 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5107941 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:09 PM PDT 24 |
| Finished | May 07 02:16:10 PM PDT 24 |
| Peak memory | 146460 kb |
| Host | smart-dd22f17d-ca66-4fde-b98d-9e3f5106fe91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622077814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.622077814 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.4160403995 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4686961 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:02 PM PDT 24 |
| Finished | May 07 02:16:03 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-d730898d-a4b5-4b94-9c69-1f45025066bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160403995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4160403995 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1566630981 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4671903 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:23 PM PDT 24 |
| Finished | May 07 02:16:24 PM PDT 24 |
| Peak memory | 146480 kb |
| Host | smart-85bee6b5-0242-4877-a6d8-d3d0ee3aad59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566630981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1566630981 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2142342142 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4887062 ps |
| CPU time | 0.36 seconds |
| Started | May 07 02:16:20 PM PDT 24 |
| Finished | May 07 02:16:21 PM PDT 24 |
| Peak memory | 146504 kb |
| Host | smart-8cebd046-34dd-4d0d-9c4d-b344909b8f5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142342142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2142342142 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.434954394 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4573722 ps |
| CPU time | 0.42 seconds |
| Started | May 07 02:16:21 PM PDT 24 |
| Finished | May 07 02:16:22 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-a7ded1c1-d46f-45f7-8ec6-779bbf1ddf6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434954394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.434954394 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4213409807 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4525619 ps |
| CPU time | 0.36 seconds |
| Started | May 07 02:16:20 PM PDT 24 |
| Finished | May 07 02:16:21 PM PDT 24 |
| Peak memory | 146448 kb |
| Host | smart-4d3c1f0b-465a-459c-bbfc-a84d580336f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213409807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4213409807 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.4017495094 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4787077 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:24 PM PDT 24 |
| Finished | May 07 02:16:25 PM PDT 24 |
| Peak memory | 146512 kb |
| Host | smart-af35fbf9-46ff-4927-b29b-6f6fe568e3fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017495094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4017495094 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.238245831 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4523399 ps |
| CPU time | 0.42 seconds |
| Started | May 07 02:16:25 PM PDT 24 |
| Finished | May 07 02:16:26 PM PDT 24 |
| Peak memory | 146452 kb |
| Host | smart-4f531787-3d91-42da-a65d-fe1b646e7024 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238245831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.238245831 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1399100327 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4756909 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:24 PM PDT 24 |
| Finished | May 07 02:16:25 PM PDT 24 |
| Peak memory | 146500 kb |
| Host | smart-ad08d015-22fb-4ca2-9626-c97808fed0ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399100327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1399100327 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.538818373 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5274027 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:25 PM PDT 24 |
| Finished | May 07 02:16:26 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-9087a286-091e-444b-a721-630a93e2cbda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=538818373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.538818373 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2779743478 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4903642 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:31 PM PDT 24 |
| Finished | May 07 02:16:32 PM PDT 24 |
| Peak memory | 146496 kb |
| Host | smart-ddbbe96f-d59d-42f5-bb65-9f639faa8c97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779743478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2779743478 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1954790105 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5272643 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:12 PM PDT 24 |
| Finished | May 07 02:16:13 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-808b9440-4979-4d32-ad7b-96a604647698 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954790105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1954790105 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2391838531 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5009973 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:14 PM PDT 24 |
| Finished | May 07 02:16:15 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-0316e8b4-f7e9-414d-b785-961bbfb90800 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391838531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2391838531 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.234012953 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4891306 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:15 PM PDT 24 |
| Finished | May 07 02:16:16 PM PDT 24 |
| Peak memory | 146464 kb |
| Host | smart-eb5ebb85-d654-432d-9b38-110514041c90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234012953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.234012953 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4195006551 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5027929 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:15 PM PDT 24 |
| Finished | May 07 02:16:16 PM PDT 24 |
| Peak memory | 146512 kb |
| Host | smart-1234ef87-6f03-40c7-a11f-b34915434279 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195006551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4195006551 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3371768515 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4694232 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:14 PM PDT 24 |
| Finished | May 07 02:16:15 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-a7659a2e-0914-4a92-8b9f-81601f8a1646 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371768515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3371768515 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2883037898 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4714775 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:19 PM PDT 24 |
| Finished | May 07 02:16:20 PM PDT 24 |
| Peak memory | 146428 kb |
| Host | smart-ab07e524-ae3c-45aa-8a67-c9a60e20eb37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883037898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2883037898 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |