| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/17.prim_esc_test.2455496209 |
| 88.27 | 2.74 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.2709962986 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.320948898 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.1252174436 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1770235646 |
| /workspace/coverage/default/1.prim_esc_test.38161900 |
| /workspace/coverage/default/10.prim_esc_test.3176736474 |
| /workspace/coverage/default/13.prim_esc_test.2003383615 |
| /workspace/coverage/default/14.prim_esc_test.2827373022 |
| /workspace/coverage/default/15.prim_esc_test.1723214168 |
| /workspace/coverage/default/16.prim_esc_test.526096397 |
| /workspace/coverage/default/18.prim_esc_test.3226670994 |
| /workspace/coverage/default/19.prim_esc_test.2644489845 |
| /workspace/coverage/default/2.prim_esc_test.1441245939 |
| /workspace/coverage/default/4.prim_esc_test.4753564 |
| /workspace/coverage/default/5.prim_esc_test.3673603676 |
| /workspace/coverage/default/6.prim_esc_test.2421897711 |
| /workspace/coverage/default/7.prim_esc_test.809292102 |
| /workspace/coverage/default/8.prim_esc_test.3946118978 |
| /workspace/coverage/default/9.prim_esc_test.1950920542 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_esc_test.2827373022 | May 09 02:04:03 PM PDT 24 | May 09 02:04:05 PM PDT 24 | 5197628 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.38161900 | May 09 02:03:53 PM PDT 24 | May 09 02:03:55 PM PDT 24 | 4879022 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.809292102 | May 09 02:04:04 PM PDT 24 | May 09 02:04:06 PM PDT 24 | 4416535 ps | ||
| T4 | /workspace/coverage/default/15.prim_esc_test.1723214168 | May 09 02:04:05 PM PDT 24 | May 09 02:04:07 PM PDT 24 | 5269078 ps | ||
| T5 | /workspace/coverage/default/5.prim_esc_test.3673603676 | May 09 02:04:04 PM PDT 24 | May 09 02:04:06 PM PDT 24 | 4544542 ps | ||
| T6 | /workspace/coverage/default/10.prim_esc_test.3176736474 | May 09 02:04:05 PM PDT 24 | May 09 02:04:07 PM PDT 24 | 5189740 ps | ||
| T9 | /workspace/coverage/default/17.prim_esc_test.2455496209 | May 09 02:04:04 PM PDT 24 | May 09 02:04:06 PM PDT 24 | 4876984 ps | ||
| T7 | /workspace/coverage/default/3.prim_esc_test.2709962986 | May 09 02:04:03 PM PDT 24 | May 09 02:04:05 PM PDT 24 | 5302180 ps | ||
| T14 | /workspace/coverage/default/2.prim_esc_test.1441245939 | May 09 02:03:53 PM PDT 24 | May 09 02:03:55 PM PDT 24 | 4547820 ps | ||
| T15 | /workspace/coverage/default/8.prim_esc_test.3946118978 | May 09 02:04:03 PM PDT 24 | May 09 02:04:04 PM PDT 24 | 5025595 ps | ||
| T16 | /workspace/coverage/default/13.prim_esc_test.2003383615 | May 09 02:04:03 PM PDT 24 | May 09 02:04:06 PM PDT 24 | 4904630 ps | ||
| T17 | /workspace/coverage/default/0.prim_esc_test.1770235646 | May 09 02:03:53 PM PDT 24 | May 09 02:03:55 PM PDT 24 | 5402569 ps | ||
| T13 | /workspace/coverage/default/12.prim_esc_test.1252174436 | May 09 02:04:05 PM PDT 24 | May 09 02:04:07 PM PDT 24 | 4987243 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.3226670994 | May 09 02:04:06 PM PDT 24 | May 09 02:04:08 PM PDT 24 | 5029925 ps | ||
| T8 | /workspace/coverage/default/16.prim_esc_test.526096397 | May 09 02:04:04 PM PDT 24 | May 09 02:04:06 PM PDT 24 | 4803202 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.4753564 | May 09 02:04:03 PM PDT 24 | May 09 02:04:04 PM PDT 24 | 4276817 ps | ||
| T10 | /workspace/coverage/default/9.prim_esc_test.1950920542 | May 09 02:04:04 PM PDT 24 | May 09 02:04:06 PM PDT 24 | 5214328 ps | ||
| T11 | /workspace/coverage/default/11.prim_esc_test.320948898 | May 09 02:04:02 PM PDT 24 | May 09 02:04:04 PM PDT 24 | 4788120 ps | ||
| T12 | /workspace/coverage/default/19.prim_esc_test.2644489845 | May 09 02:04:02 PM PDT 24 | May 09 02:04:04 PM PDT 24 | 4870943 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.2421897711 | May 09 02:04:10 PM PDT 24 | May 09 02:04:11 PM PDT 24 | 4785381 ps |
| Test location | /workspace/coverage/default/17.prim_esc_test.2455496209 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4876984 ps |
| CPU time | 0.37 seconds |
| Started | May 09 02:04:04 PM PDT 24 |
| Finished | May 09 02:04:06 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-ee065edc-5c02-4ca2-9ecc-a9282d93e503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455496209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2455496209 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2709962986 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5302180 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:03 PM PDT 24 |
| Finished | May 09 02:04:05 PM PDT 24 |
| Peak memory | 146168 kb |
| Host | smart-65ae7988-0eeb-4e99-a2fd-eb0190493d5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709962986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2709962986 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.320948898 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4788120 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:02 PM PDT 24 |
| Finished | May 09 02:04:04 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-15cc5d52-9291-408e-950b-5dafe07cf923 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320948898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.320948898 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1252174436 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4987243 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:05 PM PDT 24 |
| Finished | May 09 02:04:07 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-c79b39ca-258b-4dc8-8f14-b8e0f9bb2b6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252174436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1252174436 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1770235646 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5402569 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:03:53 PM PDT 24 |
| Finished | May 09 02:03:55 PM PDT 24 |
| Peak memory | 146220 kb |
| Host | smart-223fa5a1-d049-4e84-99f0-f35531fb7433 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770235646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1770235646 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.38161900 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4879022 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:03:53 PM PDT 24 |
| Finished | May 09 02:03:55 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-80b9db01-40f5-42fe-aa43-6e2800a22160 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38161900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.38161900 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3176736474 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5189740 ps |
| CPU time | 0.37 seconds |
| Started | May 09 02:04:05 PM PDT 24 |
| Finished | May 09 02:04:07 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-24c7527d-bbaa-4482-b9f3-f1733bef6bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176736474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3176736474 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2003383615 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4904630 ps |
| CPU time | 0.39 seconds |
| Started | May 09 02:04:03 PM PDT 24 |
| Finished | May 09 02:04:06 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-15e57d3d-884c-42c6-baa5-c9190e586700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003383615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2003383615 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2827373022 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5197628 ps |
| CPU time | 0.43 seconds |
| Started | May 09 02:04:03 PM PDT 24 |
| Finished | May 09 02:04:05 PM PDT 24 |
| Peak memory | 146252 kb |
| Host | smart-44f29a6a-9d16-4951-9e67-5624161cd9b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827373022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2827373022 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1723214168 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5269078 ps |
| CPU time | 0.39 seconds |
| Started | May 09 02:04:05 PM PDT 24 |
| Finished | May 09 02:04:07 PM PDT 24 |
| Peak memory | 146188 kb |
| Host | smart-46d219c6-317a-45be-9322-054ea4a2d779 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723214168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1723214168 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.526096397 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4803202 ps |
| CPU time | 0.4 seconds |
| Started | May 09 02:04:04 PM PDT 24 |
| Finished | May 09 02:04:06 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-ae887369-0a94-43c6-984a-c085cb3434cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526096397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.526096397 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3226670994 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5029925 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:06 PM PDT 24 |
| Finished | May 09 02:04:08 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-63c8c690-e1ab-46b3-b658-e74e1a7a1eed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226670994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3226670994 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2644489845 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4870943 ps |
| CPU time | 0.4 seconds |
| Started | May 09 02:04:02 PM PDT 24 |
| Finished | May 09 02:04:04 PM PDT 24 |
| Peak memory | 146220 kb |
| Host | smart-06f545c4-ea07-4115-b34a-7fb1537aaabd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644489845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2644489845 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1441245939 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4547820 ps |
| CPU time | 0.37 seconds |
| Started | May 09 02:03:53 PM PDT 24 |
| Finished | May 09 02:03:55 PM PDT 24 |
| Peak memory | 146220 kb |
| Host | smart-38621c05-e3f0-4ccc-9109-6c6796e4a291 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441245939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1441245939 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.4753564 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4276817 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:03 PM PDT 24 |
| Finished | May 09 02:04:04 PM PDT 24 |
| Peak memory | 146180 kb |
| Host | smart-2e2bbbd4-b69b-487e-abb8-b6e49e84a98b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4753564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.4753564 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3673603676 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4544542 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:04 PM PDT 24 |
| Finished | May 09 02:04:06 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-f63435a1-0ccf-46d6-8525-abc4a79e927f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673603676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3673603676 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2421897711 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4785381 ps |
| CPU time | 0.39 seconds |
| Started | May 09 02:04:10 PM PDT 24 |
| Finished | May 09 02:04:11 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-70f82702-ab43-42af-812e-7f2f814d4281 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421897711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2421897711 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.809292102 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4416535 ps |
| CPU time | 0.38 seconds |
| Started | May 09 02:04:04 PM PDT 24 |
| Finished | May 09 02:04:06 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-d0bc6d91-2cc5-4fdc-85bc-25f925b6942c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809292102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.809292102 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3946118978 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5025595 ps |
| CPU time | 0.37 seconds |
| Started | May 09 02:04:03 PM PDT 24 |
| Finished | May 09 02:04:04 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-76b9d221-f438-4bb8-ba7f-bf69a4152687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946118978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3946118978 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1950920542 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5214328 ps |
| CPU time | 0.4 seconds |
| Started | May 09 02:04:04 PM PDT 24 |
| Finished | May 09 02:04:06 PM PDT 24 |
| Peak memory | 146176 kb |
| Host | smart-c2b1a38c-d954-48f8-be2f-1051c89d747d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950920542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1950920542 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |