| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 88.11 | 92.38 | 85.37 | 100.00 | 85.71 | 83.72 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.83 | 84.83 | 90.48 | 90.48 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/0.prim_esc_test.117898370 |
| 86.56 | 1.74 | 91.43 | 0.95 | 82.93 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 81.40 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.1079214058 |
| 88.11 | 1.55 | 92.38 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 3.57 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3798551150 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.2199715449 |
| /workspace/coverage/default/11.prim_esc_test.2116277706 |
| /workspace/coverage/default/12.prim_esc_test.1650303847 |
| /workspace/coverage/default/13.prim_esc_test.1192885050 |
| /workspace/coverage/default/14.prim_esc_test.837894966 |
| /workspace/coverage/default/16.prim_esc_test.2187777724 |
| /workspace/coverage/default/17.prim_esc_test.683667945 |
| /workspace/coverage/default/18.prim_esc_test.2986239496 |
| /workspace/coverage/default/19.prim_esc_test.3728822856 |
| /workspace/coverage/default/2.prim_esc_test.2838504011 |
| /workspace/coverage/default/3.prim_esc_test.1149167997 |
| /workspace/coverage/default/4.prim_esc_test.1201440231 |
| /workspace/coverage/default/5.prim_esc_test.4236200924 |
| /workspace/coverage/default/6.prim_esc_test.322731748 |
| /workspace/coverage/default/7.prim_esc_test.729284116 |
| /workspace/coverage/default/8.prim_esc_test.2274899552 |
| /workspace/coverage/default/9.prim_esc_test.3766252063 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_esc_test.4236200924 | May 12 12:21:01 PM PDT 24 | May 12 12:21:02 PM PDT 24 | 4590744 ps | ||
| T2 | /workspace/coverage/default/13.prim_esc_test.1192885050 | May 12 12:21:01 PM PDT 24 | May 12 12:21:02 PM PDT 24 | 4992201 ps | ||
| T3 | /workspace/coverage/default/19.prim_esc_test.3728822856 | May 12 12:21:02 PM PDT 24 | May 12 12:21:04 PM PDT 24 | 4798663 ps | ||
| T4 | /workspace/coverage/default/18.prim_esc_test.2986239496 | May 12 12:21:01 PM PDT 24 | May 12 12:21:03 PM PDT 24 | 4497078 ps | ||
| T5 | /workspace/coverage/default/0.prim_esc_test.117898370 | May 12 12:21:01 PM PDT 24 | May 12 12:21:02 PM PDT 24 | 4396683 ps | ||
| T6 | /workspace/coverage/default/12.prim_esc_test.1650303847 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4788317 ps | ||
| T7 | /workspace/coverage/default/9.prim_esc_test.3766252063 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4513677 ps | ||
| T8 | /workspace/coverage/default/7.prim_esc_test.729284116 | May 12 12:21:02 PM PDT 24 | May 12 12:21:03 PM PDT 24 | 5589899 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.2116277706 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4781876 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.2199715449 | May 12 12:21:00 PM PDT 24 | May 12 12:21:02 PM PDT 24 | 5105050 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.2838504011 | May 12 12:21:02 PM PDT 24 | May 12 12:21:04 PM PDT 24 | 5052172 ps | ||
| T14 | /workspace/coverage/default/16.prim_esc_test.2187777724 | May 12 12:21:02 PM PDT 24 | May 12 12:21:03 PM PDT 24 | 5320875 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.3798551150 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4859368 ps | ||
| T16 | /workspace/coverage/default/3.prim_esc_test.1149167997 | May 12 12:21:01 PM PDT 24 | May 12 12:21:02 PM PDT 24 | 4331570 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.1079214058 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4628477 ps | ||
| T17 | /workspace/coverage/default/8.prim_esc_test.2274899552 | May 12 12:20:50 PM PDT 24 | May 12 12:20:51 PM PDT 24 | 5049471 ps | ||
| T18 | /workspace/coverage/default/6.prim_esc_test.322731748 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4449989 ps | ||
| T19 | /workspace/coverage/default/14.prim_esc_test.837894966 | May 12 12:21:01 PM PDT 24 | May 12 12:21:03 PM PDT 24 | 5031108 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.683667945 | May 12 12:21:01 PM PDT 24 | May 12 12:21:02 PM PDT 24 | 4771621 ps | ||
| T13 | /workspace/coverage/default/4.prim_esc_test.1201440231 | May 12 12:21:05 PM PDT 24 | May 12 12:21:06 PM PDT 24 | 4933280 ps |
| Test location | /workspace/coverage/default/0.prim_esc_test.117898370 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4396683 ps |
| CPU time | 0.36 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:02 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-17bf9885-1def-4dc9-b94c-84e7bf6a812c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117898370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.117898370 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1079214058 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4628477 ps |
| CPU time | 0.49 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 143480 kb |
| Host | smart-605e928a-44a8-4cfb-957c-5c08e36b1882 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079214058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1079214058 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3798551150 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4859368 ps |
| CPU time | 0.48 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 143164 kb |
| Host | smart-77a0e420-44eb-4a0c-8d12-74bec856e19c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3798551150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3798551150 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2199715449 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5105050 ps |
| CPU time | 0.41 seconds |
| Started | May 12 12:21:00 PM PDT 24 |
| Finished | May 12 12:21:02 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-23ea6156-902a-471d-9b43-79a8e9a376ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199715449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2199715449 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2116277706 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4781876 ps |
| CPU time | 0.5 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 143504 kb |
| Host | smart-029e6ecd-4a16-46ed-b0cb-cb3286c17c9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116277706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2116277706 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1650303847 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4788317 ps |
| CPU time | 0.48 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 143000 kb |
| Host | smart-141a2fec-53e0-43a0-a228-e836f355d2e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650303847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1650303847 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1192885050 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4992201 ps |
| CPU time | 0.37 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:02 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-78b793c2-f9d9-46c5-9055-9b5c76b97202 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192885050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1192885050 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.837894966 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5031108 ps |
| CPU time | 0.36 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:03 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-27954005-da82-45bc-85ab-14d0290f0e7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837894966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.837894966 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2187777724 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5320875 ps |
| CPU time | 0.41 seconds |
| Started | May 12 12:21:02 PM PDT 24 |
| Finished | May 12 12:21:03 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-90605566-56d7-466b-a1a4-e7e9f1d47535 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187777724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2187777724 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.683667945 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4771621 ps |
| CPU time | 0.37 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:02 PM PDT 24 |
| Peak memory | 145384 kb |
| Host | smart-a76f1f7f-0fe9-4a1d-a5d0-061e9801b383 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683667945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.683667945 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2986239496 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4497078 ps |
| CPU time | 0.37 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:03 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-05901c2c-f1fb-4973-bf39-f1567053fce9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986239496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2986239496 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3728822856 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4798663 ps |
| CPU time | 0.42 seconds |
| Started | May 12 12:21:02 PM PDT 24 |
| Finished | May 12 12:21:04 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-802df6bd-8e35-4372-b2f3-2e0ff7c7e4fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728822856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3728822856 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2838504011 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5052172 ps |
| CPU time | 0.4 seconds |
| Started | May 12 12:21:02 PM PDT 24 |
| Finished | May 12 12:21:04 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-01b35dd0-fc04-425c-9839-d9e001698d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838504011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2838504011 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1149167997 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4331570 ps |
| CPU time | 0.38 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:02 PM PDT 24 |
| Peak memory | 145352 kb |
| Host | smart-ab8525da-6e63-498b-b253-69c85d8f7680 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149167997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1149167997 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1201440231 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4933280 ps |
| CPU time | 0.48 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 143088 kb |
| Host | smart-46ab9f0c-ff2a-47a3-9fe8-8fa4034f8e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201440231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1201440231 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.4236200924 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4590744 ps |
| CPU time | 0.38 seconds |
| Started | May 12 12:21:01 PM PDT 24 |
| Finished | May 12 12:21:02 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-5b4caf57-0ae6-4153-b9e8-25341b7c4943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236200924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4236200924 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.322731748 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4449989 ps |
| CPU time | 0.48 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 143308 kb |
| Host | smart-b6ad15e7-6f95-4959-8e22-1989705a88fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322731748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.322731748 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.729284116 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5589899 ps |
| CPU time | 0.39 seconds |
| Started | May 12 12:21:02 PM PDT 24 |
| Finished | May 12 12:21:03 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-f8c7f0a6-4441-4e8f-9865-4ce0723b6c5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729284116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.729284116 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2274899552 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5049471 ps |
| CPU time | 0.42 seconds |
| Started | May 12 12:20:50 PM PDT 24 |
| Finished | May 12 12:20:51 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-d36073d2-aacd-419f-86a4-ae67651e769d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274899552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2274899552 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3766252063 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4513677 ps |
| CPU time | 0.48 seconds |
| Started | May 12 12:21:05 PM PDT 24 |
| Finished | May 12 12:21:06 PM PDT 24 |
| Peak memory | 142492 kb |
| Host | smart-9508ed98-cfd3-4c17-9096-c5c1cc85bd1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766252063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3766252063 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |