| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.53 | 86.53 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/4.prim_esc_test.1303183595 |
| 88.27 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.2455075919 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.3260757566 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2430419329 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.3574335319 |
| /workspace/coverage/default/11.prim_esc_test.3118911271 |
| /workspace/coverage/default/12.prim_esc_test.2992147985 |
| /workspace/coverage/default/13.prim_esc_test.2667577983 |
| /workspace/coverage/default/14.prim_esc_test.930487376 |
| /workspace/coverage/default/15.prim_esc_test.4162577680 |
| /workspace/coverage/default/16.prim_esc_test.2556005883 |
| /workspace/coverage/default/17.prim_esc_test.2675601063 |
| /workspace/coverage/default/18.prim_esc_test.2086295274 |
| /workspace/coverage/default/2.prim_esc_test.946210907 |
| /workspace/coverage/default/3.prim_esc_test.835670206 |
| /workspace/coverage/default/5.prim_esc_test.2639457104 |
| /workspace/coverage/default/6.prim_esc_test.820481432 |
| /workspace/coverage/default/7.prim_esc_test.2029622570 |
| /workspace/coverage/default/8.prim_esc_test.50715477 |
| /workspace/coverage/default/9.prim_esc_test.3481837944 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_esc_test.2556005883 | May 14 12:19:03 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 4687526 ps | ||
| T2 | /workspace/coverage/default/19.prim_esc_test.3260757566 | May 14 12:23:19 PM PDT 24 | May 14 12:23:21 PM PDT 24 | 5289577 ps | ||
| T3 | /workspace/coverage/default/13.prim_esc_test.2667577983 | May 14 12:19:04 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 4732666 ps | ||
| T7 | /workspace/coverage/default/0.prim_esc_test.2430419329 | May 14 12:18:54 PM PDT 24 | May 14 12:18:56 PM PDT 24 | 4809139 ps | ||
| T4 | /workspace/coverage/default/9.prim_esc_test.3481837944 | May 14 12:19:03 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 5029392 ps | ||
| T5 | /workspace/coverage/default/1.prim_esc_test.2455075919 | May 14 12:18:56 PM PDT 24 | May 14 12:18:58 PM PDT 24 | 4731862 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.1303183595 | May 14 12:18:55 PM PDT 24 | May 14 12:18:58 PM PDT 24 | 4280193 ps | ||
| T12 | /workspace/coverage/default/18.prim_esc_test.2086295274 | May 14 12:22:47 PM PDT 24 | May 14 12:22:48 PM PDT 24 | 4014104 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.3574335319 | May 14 12:19:04 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 5147248 ps | ||
| T11 | /workspace/coverage/default/14.prim_esc_test.930487376 | May 14 12:19:03 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 4687857 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.835670206 | May 14 12:18:56 PM PDT 24 | May 14 12:18:59 PM PDT 24 | 5066828 ps | ||
| T8 | /workspace/coverage/default/17.prim_esc_test.2675601063 | May 14 12:19:03 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 5075443 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.3118911271 | May 14 12:18:56 PM PDT 24 | May 14 12:18:59 PM PDT 24 | 4910464 ps | ||
| T14 | /workspace/coverage/default/8.prim_esc_test.50715477 | May 14 12:18:56 PM PDT 24 | May 14 12:18:58 PM PDT 24 | 4896751 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.4162577680 | May 14 12:19:03 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 5299431 ps | ||
| T16 | /workspace/coverage/default/5.prim_esc_test.2639457104 | May 14 12:18:56 PM PDT 24 | May 14 12:18:59 PM PDT 24 | 4989399 ps | ||
| T17 | /workspace/coverage/default/12.prim_esc_test.2992147985 | May 14 12:19:03 PM PDT 24 | May 14 12:19:06 PM PDT 24 | 5289269 ps | ||
| T18 | /workspace/coverage/default/6.prim_esc_test.820481432 | May 14 12:18:54 PM PDT 24 | May 14 12:18:56 PM PDT 24 | 4883951 ps | ||
| T19 | /workspace/coverage/default/7.prim_esc_test.2029622570 | May 14 12:18:55 PM PDT 24 | May 14 12:18:57 PM PDT 24 | 4748284 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.946210907 | May 14 12:18:55 PM PDT 24 | May 14 12:18:57 PM PDT 24 | 5527147 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.1303183595 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4280193 ps |
| CPU time | 0.36 seconds |
| Started | May 14 12:18:55 PM PDT 24 |
| Finished | May 14 12:18:58 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-f8935895-6638-4919-8097-cefc74407cee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303183595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1303183595 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2455075919 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4731862 ps |
| CPU time | 0.37 seconds |
| Started | May 14 12:18:56 PM PDT 24 |
| Finished | May 14 12:18:58 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-85d8968b-042e-4840-90bc-e77e902c7304 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455075919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2455075919 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3260757566 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5289577 ps |
| CPU time | 0.45 seconds |
| Started | May 14 12:23:19 PM PDT 24 |
| Finished | May 14 12:23:21 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-cbe7d29e-0020-41f1-9583-0dff4f828306 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260757566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3260757566 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2430419329 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4809139 ps |
| CPU time | 0.42 seconds |
| Started | May 14 12:18:54 PM PDT 24 |
| Finished | May 14 12:18:56 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-ae6deb0f-44e7-4689-90cc-708b323dc2cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430419329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2430419329 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3574335319 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5147248 ps |
| CPU time | 0.37 seconds |
| Started | May 14 12:19:04 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-710336e7-4135-4cb1-b5f7-1e65070b5ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574335319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3574335319 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3118911271 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4910464 ps |
| CPU time | 0.42 seconds |
| Started | May 14 12:18:56 PM PDT 24 |
| Finished | May 14 12:18:59 PM PDT 24 |
| Peak memory | 144648 kb |
| Host | smart-4716bc82-1fde-4c67-98f0-e8a2f1dd46c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118911271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3118911271 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2992147985 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5289269 ps |
| CPU time | 0.44 seconds |
| Started | May 14 12:19:03 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 142576 kb |
| Host | smart-72a5f89f-c1ec-469b-9326-809dabc26783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992147985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2992147985 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2667577983 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4732666 ps |
| CPU time | 0.37 seconds |
| Started | May 14 12:19:04 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-1234261a-83a9-44be-924b-0e9358d737a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667577983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2667577983 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.930487376 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4687857 ps |
| CPU time | 0.39 seconds |
| Started | May 14 12:19:03 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-82ec40ee-4cac-45ee-8c79-1d8ae1e53e04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930487376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.930487376 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4162577680 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5299431 ps |
| CPU time | 0.44 seconds |
| Started | May 14 12:19:03 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 143832 kb |
| Host | smart-158cde57-1677-4ce5-87cc-ca2cc7ebb2b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162577680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4162577680 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2556005883 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4687526 ps |
| CPU time | 0.45 seconds |
| Started | May 14 12:19:03 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 143272 kb |
| Host | smart-a25fbfaa-ed67-463c-bccb-c20dbb2c3332 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556005883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2556005883 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2675601063 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5075443 ps |
| CPU time | 0.45 seconds |
| Started | May 14 12:19:03 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 143520 kb |
| Host | smart-db5eeff3-8a2b-413a-92c7-2e7d9e1d4aab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2675601063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2675601063 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2086295274 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4014104 ps |
| CPU time | 0.39 seconds |
| Started | May 14 12:22:47 PM PDT 24 |
| Finished | May 14 12:22:48 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-e0ecba49-81eb-47d6-8b58-f286cd921d86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086295274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2086295274 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.946210907 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5527147 ps |
| CPU time | 0.43 seconds |
| Started | May 14 12:18:55 PM PDT 24 |
| Finished | May 14 12:18:57 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-13612b5d-a585-4e97-8e58-22557ebd48e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946210907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.946210907 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.835670206 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5066828 ps |
| CPU time | 0.37 seconds |
| Started | May 14 12:18:56 PM PDT 24 |
| Finished | May 14 12:18:59 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-a081e52a-f497-45f7-b431-c6d947950da7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835670206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.835670206 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2639457104 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4989399 ps |
| CPU time | 0.36 seconds |
| Started | May 14 12:18:56 PM PDT 24 |
| Finished | May 14 12:18:59 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-60b3666a-d29a-468a-99a0-772b71053991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639457104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2639457104 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.820481432 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4883951 ps |
| CPU time | 0.45 seconds |
| Started | May 14 12:18:54 PM PDT 24 |
| Finished | May 14 12:18:56 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-b29d110e-e975-447c-8309-0ccc99b9c33d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820481432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.820481432 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2029622570 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4748284 ps |
| CPU time | 0.36 seconds |
| Started | May 14 12:18:55 PM PDT 24 |
| Finished | May 14 12:18:57 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-53527122-f8f7-49a0-920f-9459374ccbf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029622570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2029622570 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.50715477 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4896751 ps |
| CPU time | 0.37 seconds |
| Started | May 14 12:18:56 PM PDT 24 |
| Finished | May 14 12:18:58 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-15c74003-2809-480e-9277-878a230b8f17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50715477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.50715477 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3481837944 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5029392 ps |
| CPU time | 0.46 seconds |
| Started | May 14 12:19:03 PM PDT 24 |
| Finished | May 14 12:19:06 PM PDT 24 |
| Peak memory | 144244 kb |
| Host | smart-5c22dba2-014c-41bc-93ca-af405940d63c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481837944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3481837944 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |