| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/0.prim_esc_test.4149505195 |
| 88.27 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1978570033 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.1738859728 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.4218728284 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.3665638919 |
| /workspace/coverage/default/12.prim_esc_test.895157207 |
| /workspace/coverage/default/13.prim_esc_test.92198394 |
| /workspace/coverage/default/14.prim_esc_test.2038473180 |
| /workspace/coverage/default/15.prim_esc_test.1157935335 |
| /workspace/coverage/default/16.prim_esc_test.821321700 |
| /workspace/coverage/default/17.prim_esc_test.760943357 |
| /workspace/coverage/default/19.prim_esc_test.3964946951 |
| /workspace/coverage/default/2.prim_esc_test.2502330931 |
| /workspace/coverage/default/3.prim_esc_test.2886052356 |
| /workspace/coverage/default/4.prim_esc_test.724598797 |
| /workspace/coverage/default/5.prim_esc_test.2894407063 |
| /workspace/coverage/default/6.prim_esc_test.4018205517 |
| /workspace/coverage/default/7.prim_esc_test.1681751239 |
| /workspace/coverage/default/8.prim_esc_test.3692046217 |
| /workspace/coverage/default/9.prim_esc_test.2491469048 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_esc_test.1978570033 | May 16 12:18:40 PM PDT 24 | May 16 12:18:43 PM PDT 24 | 5163915 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.4018205517 | May 16 12:18:35 PM PDT 24 | May 16 12:18:37 PM PDT 24 | 4810174 ps | ||
| T3 | /workspace/coverage/default/0.prim_esc_test.4149505195 | May 16 12:18:28 PM PDT 24 | May 16 12:18:30 PM PDT 24 | 5235630 ps | ||
| T5 | /workspace/coverage/default/8.prim_esc_test.3692046217 | May 16 12:18:34 PM PDT 24 | May 16 12:18:36 PM PDT 24 | 4991745 ps | ||
| T12 | /workspace/coverage/default/19.prim_esc_test.3964946951 | May 16 12:18:45 PM PDT 24 | May 16 12:18:49 PM PDT 24 | 4855760 ps | ||
| T9 | /workspace/coverage/default/2.prim_esc_test.2502330931 | May 16 12:18:33 PM PDT 24 | May 16 12:18:35 PM PDT 24 | 4458895 ps | ||
| T10 | /workspace/coverage/default/1.prim_esc_test.3665638919 | May 16 12:18:34 PM PDT 24 | May 16 12:18:36 PM PDT 24 | 4702831 ps | ||
| T8 | /workspace/coverage/default/5.prim_esc_test.2894407063 | May 16 12:18:33 PM PDT 24 | May 16 12:18:34 PM PDT 24 | 4331676 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.2886052356 | May 16 12:18:28 PM PDT 24 | May 16 12:18:30 PM PDT 24 | 5010860 ps | ||
| T4 | /workspace/coverage/default/12.prim_esc_test.895157207 | May 16 12:18:44 PM PDT 24 | May 16 12:18:48 PM PDT 24 | 4785678 ps | ||
| T16 | /workspace/coverage/default/7.prim_esc_test.1681751239 | May 16 12:18:26 PM PDT 24 | May 16 12:18:28 PM PDT 24 | 5494925 ps | ||
| T7 | /workspace/coverage/default/13.prim_esc_test.92198394 | May 16 12:18:44 PM PDT 24 | May 16 12:18:48 PM PDT 24 | 4713316 ps | ||
| T17 | /workspace/coverage/default/4.prim_esc_test.724598797 | May 16 12:18:26 PM PDT 24 | May 16 12:18:28 PM PDT 24 | 4815749 ps | ||
| T6 | /workspace/coverage/default/18.prim_esc_test.1738859728 | May 16 12:18:55 PM PDT 24 | May 16 12:18:56 PM PDT 24 | 4004018 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.821321700 | May 16 12:23:55 PM PDT 24 | May 16 12:24:00 PM PDT 24 | 5009026 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.4218728284 | May 16 12:18:38 PM PDT 24 | May 16 12:18:41 PM PDT 24 | 5118587 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.1157935335 | May 16 12:18:45 PM PDT 24 | May 16 12:18:49 PM PDT 24 | 4150866 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.760943357 | May 16 12:21:12 PM PDT 24 | May 16 12:21:13 PM PDT 24 | 5207072 ps | ||
| T11 | /workspace/coverage/default/9.prim_esc_test.2491469048 | May 16 12:18:26 PM PDT 24 | May 16 12:18:28 PM PDT 24 | 4671653 ps | ||
| T15 | /workspace/coverage/default/14.prim_esc_test.2038473180 | May 16 12:18:37 PM PDT 24 | May 16 12:18:39 PM PDT 24 | 4734441 ps |
| Test location | /workspace/coverage/default/0.prim_esc_test.4149505195 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5235630 ps |
| CPU time | 0.39 seconds |
| Started | May 16 12:18:28 PM PDT 24 |
| Finished | May 16 12:18:30 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-5502b5dd-6118-46df-9ae1-3f8cb521ca73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149505195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4149505195 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1978570033 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5163915 ps |
| CPU time | 0.4 seconds |
| Started | May 16 12:18:40 PM PDT 24 |
| Finished | May 16 12:18:43 PM PDT 24 |
| Peak memory | 146096 kb |
| Host | smart-b66d94a8-38f7-48e5-9378-060701380904 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978570033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1978570033 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1738859728 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4004018 ps |
| CPU time | 0.37 seconds |
| Started | May 16 12:18:55 PM PDT 24 |
| Finished | May 16 12:18:56 PM PDT 24 |
| Peak memory | 146156 kb |
| Host | smart-0f766b2d-7c54-4912-8f9d-8c10c77df132 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738859728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1738859728 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.4218728284 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5118587 ps |
| CPU time | 0.41 seconds |
| Started | May 16 12:18:38 PM PDT 24 |
| Finished | May 16 12:18:41 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-31f6b58a-eed8-4b42-9aa3-fb193d253dc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218728284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4218728284 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3665638919 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4702831 ps |
| CPU time | 0.4 seconds |
| Started | May 16 12:18:34 PM PDT 24 |
| Finished | May 16 12:18:36 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-298b0c5f-99d0-4e4c-bde5-20cf856b8ee5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665638919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3665638919 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.895157207 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4785678 ps |
| CPU time | 0.37 seconds |
| Started | May 16 12:18:44 PM PDT 24 |
| Finished | May 16 12:18:48 PM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-d520efd1-1d2a-4bd2-9d40-5b4e6db2f9f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895157207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.895157207 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.92198394 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4713316 ps |
| CPU time | 0.39 seconds |
| Started | May 16 12:18:44 PM PDT 24 |
| Finished | May 16 12:18:48 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-b07d0e8e-a046-49da-b973-99eefc3a3c28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92198394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.92198394 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2038473180 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4734441 ps |
| CPU time | 0.45 seconds |
| Started | May 16 12:18:37 PM PDT 24 |
| Finished | May 16 12:18:39 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-7a710c78-a23e-4be4-be3d-63fca9f4e67d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038473180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2038473180 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1157935335 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4150866 ps |
| CPU time | 0.37 seconds |
| Started | May 16 12:18:45 PM PDT 24 |
| Finished | May 16 12:18:49 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-17bd64af-1556-46db-91bc-f09458e83ce1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157935335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1157935335 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.821321700 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5009026 ps |
| CPU time | 0.41 seconds |
| Started | May 16 12:23:55 PM PDT 24 |
| Finished | May 16 12:24:00 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-416cffec-b926-42b9-ae12-be72edaec3e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821321700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.821321700 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.760943357 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5207072 ps |
| CPU time | 0.4 seconds |
| Started | May 16 12:21:12 PM PDT 24 |
| Finished | May 16 12:21:13 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-ad0628ea-4bcb-4b23-b931-dc77a526b413 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760943357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.760943357 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3964946951 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4855760 ps |
| CPU time | 0.38 seconds |
| Started | May 16 12:18:45 PM PDT 24 |
| Finished | May 16 12:18:49 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-ebfed63c-b099-4a23-b810-ce8710afa417 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964946951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3964946951 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2502330931 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4458895 ps |
| CPU time | 0.37 seconds |
| Started | May 16 12:18:33 PM PDT 24 |
| Finished | May 16 12:18:35 PM PDT 24 |
| Peak memory | 146116 kb |
| Host | smart-7a538b6a-4501-4817-8e3d-b9686676c33c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502330931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2502330931 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2886052356 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5010860 ps |
| CPU time | 0.38 seconds |
| Started | May 16 12:18:28 PM PDT 24 |
| Finished | May 16 12:18:30 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-9e37e9e0-57a0-4947-99c7-80a4f551e4be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886052356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2886052356 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.724598797 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4815749 ps |
| CPU time | 0.46 seconds |
| Started | May 16 12:18:26 PM PDT 24 |
| Finished | May 16 12:18:28 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-addf4cb1-b49a-4cd0-a4be-d31a309e28db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724598797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.724598797 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2894407063 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4331676 ps |
| CPU time | 0.38 seconds |
| Started | May 16 12:18:33 PM PDT 24 |
| Finished | May 16 12:18:34 PM PDT 24 |
| Peak memory | 146076 kb |
| Host | smart-deb56f3d-b8b3-4a62-971c-24ac402cdc57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894407063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2894407063 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4018205517 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4810174 ps |
| CPU time | 0.37 seconds |
| Started | May 16 12:18:35 PM PDT 24 |
| Finished | May 16 12:18:37 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-8f808de3-caf9-425f-8a10-bc708b7e3dcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018205517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4018205517 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1681751239 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5494925 ps |
| CPU time | 0.42 seconds |
| Started | May 16 12:18:26 PM PDT 24 |
| Finished | May 16 12:18:28 PM PDT 24 |
| Peak memory | 146024 kb |
| Host | smart-29fb27c0-a234-4ecf-9f48-e99de95a8b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681751239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1681751239 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3692046217 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4991745 ps |
| CPU time | 0.38 seconds |
| Started | May 16 12:18:34 PM PDT 24 |
| Finished | May 16 12:18:36 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-cefd6722-3f4f-4583-af9d-285f5e8a2791 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692046217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3692046217 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2491469048 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4671653 ps |
| CPU time | 0.41 seconds |
| Started | May 16 12:18:26 PM PDT 24 |
| Finished | May 16 12:18:28 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-dbc208ea-784f-4d71-9b63-ad24c6d5d19d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491469048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2491469048 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |