| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 88.71 | 92.38 | 85.37 | 100.00 | 89.29 | 83.72 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.83 | 84.83 | 90.48 | 90.48 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/14.prim_esc_test.459822530 |
| 86.97 | 2.14 | 91.43 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 81.40 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.794531460 |
| 88.71 | 1.74 | 92.38 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2456977154 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.47486679 |
| /workspace/coverage/default/10.prim_esc_test.2405279843 |
| /workspace/coverage/default/11.prim_esc_test.256754598 |
| /workspace/coverage/default/12.prim_esc_test.632142723 |
| /workspace/coverage/default/13.prim_esc_test.3954351952 |
| /workspace/coverage/default/15.prim_esc_test.897135237 |
| /workspace/coverage/default/16.prim_esc_test.3513505095 |
| /workspace/coverage/default/17.prim_esc_test.1439422924 |
| /workspace/coverage/default/18.prim_esc_test.32040434 |
| /workspace/coverage/default/2.prim_esc_test.1442273354 |
| /workspace/coverage/default/3.prim_esc_test.1999394597 |
| /workspace/coverage/default/4.prim_esc_test.1506649328 |
| /workspace/coverage/default/5.prim_esc_test.1597146683 |
| /workspace/coverage/default/6.prim_esc_test.2207646815 |
| /workspace/coverage/default/7.prim_esc_test.2479420558 |
| /workspace/coverage/default/8.prim_esc_test.3999827918 |
| /workspace/coverage/default/9.prim_esc_test.922096178 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/15.prim_esc_test.897135237 | May 19 12:18:03 PM PDT 24 | May 19 12:18:05 PM PDT 24 | 4375255 ps | ||
| T2 | /workspace/coverage/default/8.prim_esc_test.3999827918 | May 19 12:18:05 PM PDT 24 | May 19 12:18:06 PM PDT 24 | 4925481 ps | ||
| T3 | /workspace/coverage/default/9.prim_esc_test.922096178 | May 19 12:19:20 PM PDT 24 | May 19 12:19:21 PM PDT 24 | 5278582 ps | ||
| T6 | /workspace/coverage/default/19.prim_esc_test.794531460 | May 19 12:19:08 PM PDT 24 | May 19 12:19:11 PM PDT 24 | 4938349 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.256754598 | May 19 12:19:07 PM PDT 24 | May 19 12:19:10 PM PDT 24 | 5323167 ps | ||
| T8 | /workspace/coverage/default/6.prim_esc_test.2207646815 | May 19 12:18:11 PM PDT 24 | May 19 12:18:13 PM PDT 24 | 4846677 ps | ||
| T9 | /workspace/coverage/default/14.prim_esc_test.459822530 | May 19 12:19:08 PM PDT 24 | May 19 12:19:11 PM PDT 24 | 4643435 ps | ||
| T10 | /workspace/coverage/default/7.prim_esc_test.2479420558 | May 19 12:19:20 PM PDT 24 | May 19 12:19:21 PM PDT 24 | 4473907 ps | ||
| T11 | /workspace/coverage/default/4.prim_esc_test.1506649328 | May 19 12:18:03 PM PDT 24 | May 19 12:18:04 PM PDT 24 | 4511467 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.3513505095 | May 19 12:23:27 PM PDT 24 | May 19 12:23:47 PM PDT 24 | 4407388 ps | ||
| T15 | /workspace/coverage/default/12.prim_esc_test.632142723 | May 19 12:19:08 PM PDT 24 | May 19 12:19:10 PM PDT 24 | 5526726 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.1439422924 | May 19 12:19:10 PM PDT 24 | May 19 12:19:13 PM PDT 24 | 4655776 ps | ||
| T16 | /workspace/coverage/default/2.prim_esc_test.1442273354 | May 19 12:17:59 PM PDT 24 | May 19 12:18:00 PM PDT 24 | 4757404 ps | ||
| T17 | /workspace/coverage/default/18.prim_esc_test.32040434 | May 19 12:19:08 PM PDT 24 | May 19 12:19:10 PM PDT 24 | 4954134 ps | ||
| T18 | /workspace/coverage/default/3.prim_esc_test.1999394597 | May 19 12:17:58 PM PDT 24 | May 19 12:17:59 PM PDT 24 | 4691127 ps | ||
| T4 | /workspace/coverage/default/1.prim_esc_test.47486679 | May 19 12:17:55 PM PDT 24 | May 19 12:17:56 PM PDT 24 | 5024594 ps | ||
| T14 | /workspace/coverage/default/5.prim_esc_test.1597146683 | May 19 12:18:10 PM PDT 24 | May 19 12:18:11 PM PDT 24 | 4445964 ps | ||
| T19 | /workspace/coverage/default/13.prim_esc_test.3954351952 | May 19 12:18:11 PM PDT 24 | May 19 12:18:12 PM PDT 24 | 4361784 ps | ||
| T20 | /workspace/coverage/default/10.prim_esc_test.2405279843 | May 19 12:18:02 PM PDT 24 | May 19 12:18:03 PM PDT 24 | 4441047 ps | ||
| T5 | /workspace/coverage/default/0.prim_esc_test.2456977154 | May 19 12:18:04 PM PDT 24 | May 19 12:18:05 PM PDT 24 | 5131898 ps |
| Test location | /workspace/coverage/default/14.prim_esc_test.459822530 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4643435 ps |
| CPU time | 0.37 seconds |
| Started | May 19 12:19:08 PM PDT 24 |
| Finished | May 19 12:19:11 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-a3cf85e4-9cb0-4766-b55c-d306cd8808db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459822530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.459822530 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.794531460 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4938349 ps |
| CPU time | 0.36 seconds |
| Started | May 19 12:19:08 PM PDT 24 |
| Finished | May 19 12:19:11 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-ac42b671-c253-4500-b8fc-d1ba6a3dd456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=794531460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.794531460 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2456977154 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5131898 ps |
| CPU time | 0.41 seconds |
| Started | May 19 12:18:04 PM PDT 24 |
| Finished | May 19 12:18:05 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-ddfdfd4a-b529-4dd9-aaf9-a91d292d537b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456977154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2456977154 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.47486679 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5024594 ps |
| CPU time | 0.42 seconds |
| Started | May 19 12:17:55 PM PDT 24 |
| Finished | May 19 12:17:56 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-af8cadb4-7b0d-4b2b-8e2c-e0b271d4c8d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47486679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.47486679 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2405279843 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4441047 ps |
| CPU time | 0.41 seconds |
| Started | May 19 12:18:02 PM PDT 24 |
| Finished | May 19 12:18:03 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-ab305089-d53e-405b-a0af-86eff2f6474a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405279843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2405279843 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.256754598 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5323167 ps |
| CPU time | 0.42 seconds |
| Started | May 19 12:19:07 PM PDT 24 |
| Finished | May 19 12:19:10 PM PDT 24 |
| Peak memory | 144012 kb |
| Host | smart-882bc73a-eeb6-47dd-b1f5-eb5ad668717f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256754598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.256754598 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.632142723 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5526726 ps |
| CPU time | 0.38 seconds |
| Started | May 19 12:19:08 PM PDT 24 |
| Finished | May 19 12:19:10 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-dad85dc7-a1c1-4900-a931-53c0f03814c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632142723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.632142723 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3954351952 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4361784 ps |
| CPU time | 0.38 seconds |
| Started | May 19 12:18:11 PM PDT 24 |
| Finished | May 19 12:18:12 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-51ad556f-853f-4db3-9fde-3c746d22963a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954351952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3954351952 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.897135237 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4375255 ps |
| CPU time | 0.44 seconds |
| Started | May 19 12:18:03 PM PDT 24 |
| Finished | May 19 12:18:05 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-fd932d45-fa85-45b0-8bbd-48f1c83012dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897135237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.897135237 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3513505095 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4407388 ps |
| CPU time | 0.42 seconds |
| Started | May 19 12:23:27 PM PDT 24 |
| Finished | May 19 12:23:47 PM PDT 24 |
| Peak memory | 144404 kb |
| Host | smart-4238c1c4-14bf-43e9-a393-da0b836773f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513505095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3513505095 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1439422924 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4655776 ps |
| CPU time | 0.37 seconds |
| Started | May 19 12:19:10 PM PDT 24 |
| Finished | May 19 12:19:13 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-8a7d0e7b-6536-4d72-9ece-7eaac0050b0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439422924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1439422924 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.32040434 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4954134 ps |
| CPU time | 0.36 seconds |
| Started | May 19 12:19:08 PM PDT 24 |
| Finished | May 19 12:19:10 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-f63c2d9c-1989-47a0-9098-5d441ee1d6a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32040434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.32040434 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1442273354 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4757404 ps |
| CPU time | 0.47 seconds |
| Started | May 19 12:17:59 PM PDT 24 |
| Finished | May 19 12:18:00 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-7892e76b-1ad6-4401-b6cf-7fcd56ccdb63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442273354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1442273354 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1999394597 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4691127 ps |
| CPU time | 0.36 seconds |
| Started | May 19 12:17:58 PM PDT 24 |
| Finished | May 19 12:17:59 PM PDT 24 |
| Peak memory | 146316 kb |
| Host | smart-ffb17f2a-39c3-4eda-8e2a-8b209728d67f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999394597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1999394597 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1506649328 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4511467 ps |
| CPU time | 0.37 seconds |
| Started | May 19 12:18:03 PM PDT 24 |
| Finished | May 19 12:18:04 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-26da5684-c058-4679-a81a-fd85a7f9fc70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506649328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1506649328 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1597146683 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4445964 ps |
| CPU time | 0.39 seconds |
| Started | May 19 12:18:10 PM PDT 24 |
| Finished | May 19 12:18:11 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-d93a1394-ddab-43b3-aaa5-50d3dff0c779 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597146683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1597146683 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2207646815 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4846677 ps |
| CPU time | 0.42 seconds |
| Started | May 19 12:18:11 PM PDT 24 |
| Finished | May 19 12:18:13 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-758d847a-9146-45db-b909-f0a82a29b88d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207646815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2207646815 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2479420558 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4473907 ps |
| CPU time | 0.43 seconds |
| Started | May 19 12:19:20 PM PDT 24 |
| Finished | May 19 12:19:21 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-bde90b71-830b-4c63-9de4-f9dc1a712db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479420558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2479420558 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3999827918 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4925481 ps |
| CPU time | 0.37 seconds |
| Started | May 19 12:18:05 PM PDT 24 |
| Finished | May 19 12:18:06 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-841747fb-38cf-4abb-9fb9-262766e3ecda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999827918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3999827918 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.922096178 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5278582 ps |
| CPU time | 0.38 seconds |
| Started | May 19 12:19:20 PM PDT 24 |
| Finished | May 19 12:19:21 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-6a4076ba-8395-46dc-8a4a-4e442570aa21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922096178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.922096178 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |