| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.13 | 86.13 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.2658260035 |
| 87.86 | 1.74 | 93.33 | 0.95 | 82.93 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.1653423185 |
| 89.41 | 1.55 | 94.29 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2423595038 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.1562469827 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2763784730 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.4051867608 |
| /workspace/coverage/default/11.prim_esc_test.1606583968 |
| /workspace/coverage/default/13.prim_esc_test.727667891 |
| /workspace/coverage/default/16.prim_esc_test.3222360675 |
| /workspace/coverage/default/17.prim_esc_test.2732591870 |
| /workspace/coverage/default/18.prim_esc_test.1424112949 |
| /workspace/coverage/default/19.prim_esc_test.2486379867 |
| /workspace/coverage/default/2.prim_esc_test.2555312373 |
| /workspace/coverage/default/3.prim_esc_test.468913293 |
| /workspace/coverage/default/4.prim_esc_test.2031676151 |
| /workspace/coverage/default/5.prim_esc_test.4220375786 |
| /workspace/coverage/default/6.prim_esc_test.1411521554 |
| /workspace/coverage/default/7.prim_esc_test.4294658321 |
| /workspace/coverage/default/8.prim_esc_test.3825844918 |
| /workspace/coverage/default/9.prim_esc_test.3195579668 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_esc_test.2658260035 | May 21 12:16:02 PM PDT 24 | May 21 12:16:03 PM PDT 24 | 4609452 ps | ||
| T2 | /workspace/coverage/default/3.prim_esc_test.468913293 | May 21 12:20:31 PM PDT 24 | May 21 12:20:33 PM PDT 24 | 4992509 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.4294658321 | May 21 12:16:13 PM PDT 24 | May 21 12:16:15 PM PDT 24 | 4395320 ps | ||
| T7 | /workspace/coverage/default/15.prim_esc_test.1562469827 | May 21 12:23:14 PM PDT 24 | May 21 12:23:16 PM PDT 24 | 4318069 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.2031676151 | May 21 12:16:07 PM PDT 24 | May 21 12:16:08 PM PDT 24 | 4276296 ps | ||
| T11 | /workspace/coverage/default/9.prim_esc_test.3195579668 | May 21 12:23:13 PM PDT 24 | May 21 12:23:15 PM PDT 24 | 4943479 ps | ||
| T4 | /workspace/coverage/default/13.prim_esc_test.727667891 | May 21 12:20:34 PM PDT 24 | May 21 12:20:36 PM PDT 24 | 4749045 ps | ||
| T16 | /workspace/coverage/default/2.prim_esc_test.2555312373 | May 21 12:16:47 PM PDT 24 | May 21 12:16:48 PM PDT 24 | 4986225 ps | ||
| T9 | /workspace/coverage/default/19.prim_esc_test.2486379867 | May 21 12:16:14 PM PDT 24 | May 21 12:16:16 PM PDT 24 | 4784089 ps | ||
| T17 | /workspace/coverage/default/5.prim_esc_test.4220375786 | May 21 12:16:03 PM PDT 24 | May 21 12:16:04 PM PDT 24 | 5000888 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.2732591870 | May 21 12:16:14 PM PDT 24 | May 21 12:16:15 PM PDT 24 | 5003990 ps | ||
| T5 | /workspace/coverage/default/6.prim_esc_test.1411521554 | May 21 12:16:14 PM PDT 24 | May 21 12:16:16 PM PDT 24 | 5272839 ps | ||
| T6 | /workspace/coverage/default/10.prim_esc_test.4051867608 | May 21 12:18:25 PM PDT 24 | May 21 12:18:26 PM PDT 24 | 4295900 ps | ||
| T19 | /workspace/coverage/default/16.prim_esc_test.3222360675 | May 21 12:18:10 PM PDT 24 | May 21 12:18:12 PM PDT 24 | 4974624 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.1606583968 | May 21 12:16:14 PM PDT 24 | May 21 12:16:15 PM PDT 24 | 5103230 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.2423595038 | May 21 12:16:08 PM PDT 24 | May 21 12:16:09 PM PDT 24 | 4825607 ps | ||
| T10 | /workspace/coverage/default/8.prim_esc_test.3825844918 | May 21 12:19:48 PM PDT 24 | May 21 12:19:49 PM PDT 24 | 4662230 ps | ||
| T20 | /workspace/coverage/default/1.prim_esc_test.1653423185 | May 21 12:16:14 PM PDT 24 | May 21 12:16:16 PM PDT 24 | 5575987 ps | ||
| T14 | /workspace/coverage/default/18.prim_esc_test.1424112949 | May 21 12:22:38 PM PDT 24 | May 21 12:22:41 PM PDT 24 | 4874509 ps | ||
| T18 | /workspace/coverage/default/14.prim_esc_test.2763784730 | May 21 12:16:14 PM PDT 24 | May 21 12:16:16 PM PDT 24 | 4824928 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.2658260035 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4609452 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:16:02 PM PDT 24 |
| Finished | May 21 12:16:03 PM PDT 24 |
| Peak memory | 146008 kb |
| Host | smart-bf12f30a-9935-45e2-95b6-6bd9498994fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658260035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2658260035 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1653423185 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5575987 ps |
| CPU time | 0.48 seconds |
| Started | May 21 12:16:14 PM PDT 24 |
| Finished | May 21 12:16:16 PM PDT 24 |
| Peak memory | 144424 kb |
| Host | smart-3aa53ee6-cd03-46c1-a466-e2d404fc3808 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653423185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1653423185 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2423595038 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4825607 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:16:08 PM PDT 24 |
| Finished | May 21 12:16:09 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-2e031832-52dc-4be4-8aff-dac46f77fd64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423595038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2423595038 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1562469827 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4318069 ps |
| CPU time | 0.36 seconds |
| Started | May 21 12:23:14 PM PDT 24 |
| Finished | May 21 12:23:16 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-96abf058-b3e0-477e-9d72-090f6b1acedd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562469827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1562469827 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2763784730 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4824928 ps |
| CPU time | 0.37 seconds |
| Started | May 21 12:16:14 PM PDT 24 |
| Finished | May 21 12:16:16 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-93dc4ad9-5fea-4336-92a1-dd45063baed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763784730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2763784730 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.4051867608 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4295900 ps |
| CPU time | 0.44 seconds |
| Started | May 21 12:18:25 PM PDT 24 |
| Finished | May 21 12:18:26 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-498fa927-9c97-407e-b3cf-8bec2f8ea288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051867608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4051867608 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1606583968 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5103230 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:16:14 PM PDT 24 |
| Finished | May 21 12:16:15 PM PDT 24 |
| Peak memory | 146672 kb |
| Host | smart-355e69f9-f9b0-495d-8f50-d75a2b361763 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606583968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1606583968 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.727667891 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4749045 ps |
| CPU time | 0.45 seconds |
| Started | May 21 12:20:34 PM PDT 24 |
| Finished | May 21 12:20:36 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-3337109f-670b-4a6b-8c9b-41889d396cfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727667891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.727667891 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3222360675 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4974624 ps |
| CPU time | 0.42 seconds |
| Started | May 21 12:18:10 PM PDT 24 |
| Finished | May 21 12:18:12 PM PDT 24 |
| Peak memory | 145992 kb |
| Host | smart-521aaf62-1513-45a7-9697-ef6a8acb1377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222360675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3222360675 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2732591870 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5003990 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:16:14 PM PDT 24 |
| Finished | May 21 12:16:15 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-bbcb8708-506a-4cd1-81b0-940cc95c6a6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732591870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2732591870 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1424112949 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4874509 ps |
| CPU time | 0.44 seconds |
| Started | May 21 12:22:38 PM PDT 24 |
| Finished | May 21 12:22:41 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-7320f18e-e1ef-4733-bd62-599a0d511c07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424112949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1424112949 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2486379867 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4784089 ps |
| CPU time | 0.53 seconds |
| Started | May 21 12:16:14 PM PDT 24 |
| Finished | May 21 12:16:16 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-359fc96b-9600-429c-b6a2-cfa8b4a2f6de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486379867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2486379867 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2555312373 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4986225 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:16:47 PM PDT 24 |
| Finished | May 21 12:16:48 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-2b1c46c3-c7c9-4fea-aab8-879d17fbc590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555312373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2555312373 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.468913293 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4992509 ps |
| CPU time | 0.42 seconds |
| Started | May 21 12:20:31 PM PDT 24 |
| Finished | May 21 12:20:33 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-5a33f10e-3e4c-4bd0-bd7c-612d83bcd632 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468913293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.468913293 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2031676151 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4276296 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:16:07 PM PDT 24 |
| Finished | May 21 12:16:08 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-6de51c6b-228e-4e34-a505-e478a5f3465f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031676151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2031676151 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.4220375786 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5000888 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:16:03 PM PDT 24 |
| Finished | May 21 12:16:04 PM PDT 24 |
| Peak memory | 146048 kb |
| Host | smart-2c195301-5a60-4bbb-b4cb-6fb6d79eeca2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220375786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4220375786 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1411521554 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5272839 ps |
| CPU time | 0.52 seconds |
| Started | May 21 12:16:14 PM PDT 24 |
| Finished | May 21 12:16:16 PM PDT 24 |
| Peak memory | 143484 kb |
| Host | smart-c9af821b-7be4-4ed6-832a-b6d6e10f1e6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411521554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1411521554 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4294658321 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4395320 ps |
| CPU time | 0.44 seconds |
| Started | May 21 12:16:13 PM PDT 24 |
| Finished | May 21 12:16:15 PM PDT 24 |
| Peak memory | 144604 kb |
| Host | smart-ba84b79f-126d-4d5b-947e-0c803627ccec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294658321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4294658321 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3825844918 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4662230 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:19:48 PM PDT 24 |
| Finished | May 21 12:19:49 PM PDT 24 |
| Peak memory | 146832 kb |
| Host | smart-c336d4fb-bf85-45d1-910b-90f7b1f85093 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825844918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3825844918 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3195579668 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4943479 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:23:13 PM PDT 24 |
| Finished | May 21 12:23:15 PM PDT 24 |
| Peak memory | 146836 kb |
| Host | smart-bf063773-f54d-433b-897b-9e2f454bdc52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195579668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3195579668 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |