| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.53 | 84.53 | 92.38 | 92.38 | 80.49 | 80.49 | 100.00 | 100.00 | 71.43 | 71.43 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/8.prim_esc_test.3048205449 |
| 87.08 | 2.55 | 93.33 | 0.95 | 85.37 | 4.88 | 100.00 | 0.00 | 78.57 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2734800550 |
| 88.82 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.2125426680 |
| 89.96 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.575259695 |
| 90.55 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/5.prim_esc_test.3498117757 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.3986880062 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1697895630 |
| /workspace/coverage/default/1.prim_esc_test.2601411611 |
| /workspace/coverage/default/10.prim_esc_test.4171078370 |
| /workspace/coverage/default/12.prim_esc_test.1882719429 |
| /workspace/coverage/default/13.prim_esc_test.633525756 |
| /workspace/coverage/default/14.prim_esc_test.2708589128 |
| /workspace/coverage/default/15.prim_esc_test.438996695 |
| /workspace/coverage/default/16.prim_esc_test.2629389800 |
| /workspace/coverage/default/18.prim_esc_test.884719664 |
| /workspace/coverage/default/19.prim_esc_test.1803522785 |
| /workspace/coverage/default/2.prim_esc_test.3167236025 |
| /workspace/coverage/default/4.prim_esc_test.1777154550 |
| /workspace/coverage/default/6.prim_esc_test.1627570702 |
| /workspace/coverage/default/7.prim_esc_test.237586563 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_esc_test.2601411611 | May 23 12:23:46 PM PDT 24 | May 23 12:23:47 PM PDT 24 | 4831698 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.3167236025 | May 23 12:23:18 PM PDT 24 | May 23 12:23:20 PM PDT 24 | 4639466 ps | ||
| T3 | /workspace/coverage/default/12.prim_esc_test.1882719429 | May 23 12:22:00 PM PDT 24 | May 23 12:22:02 PM PDT 24 | 5012132 ps | ||
| T4 | /workspace/coverage/default/5.prim_esc_test.3498117757 | May 23 12:24:02 PM PDT 24 | May 23 12:24:03 PM PDT 24 | 5453062 ps | ||
| T12 | /workspace/coverage/default/18.prim_esc_test.884719664 | May 23 12:25:50 PM PDT 24 | May 23 12:25:52 PM PDT 24 | 5258784 ps | ||
| T11 | /workspace/coverage/default/6.prim_esc_test.1627570702 | May 23 12:25:21 PM PDT 24 | May 23 12:25:22 PM PDT 24 | 5349157 ps | ||
| T13 | /workspace/coverage/default/16.prim_esc_test.2629389800 | May 23 12:26:18 PM PDT 24 | May 23 12:26:20 PM PDT 24 | 5118808 ps | ||
| T6 | /workspace/coverage/default/13.prim_esc_test.633525756 | May 23 12:26:44 PM PDT 24 | May 23 12:26:48 PM PDT 24 | 4648327 ps | ||
| T14 | /workspace/coverage/default/10.prim_esc_test.4171078370 | May 23 12:25:21 PM PDT 24 | May 23 12:25:23 PM PDT 24 | 5260718 ps | ||
| T7 | /workspace/coverage/default/8.prim_esc_test.3048205449 | May 23 12:25:34 PM PDT 24 | May 23 12:25:36 PM PDT 24 | 5397208 ps | ||
| T15 | /workspace/coverage/default/4.prim_esc_test.1777154550 | May 23 12:24:04 PM PDT 24 | May 23 12:24:06 PM PDT 24 | 4360694 ps | ||
| T16 | /workspace/coverage/default/0.prim_esc_test.1697895630 | May 23 12:23:50 PM PDT 24 | May 23 12:23:51 PM PDT 24 | 5229632 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.2734800550 | May 23 12:25:09 PM PDT 24 | May 23 12:25:11 PM PDT 24 | 4576007 ps | ||
| T8 | /workspace/coverage/default/7.prim_esc_test.237586563 | May 23 12:24:01 PM PDT 24 | May 23 12:24:03 PM PDT 24 | 5156069 ps | ||
| T10 | /workspace/coverage/default/9.prim_esc_test.3986880062 | May 23 12:25:34 PM PDT 24 | May 23 12:25:35 PM PDT 24 | 4409624 ps | ||
| T17 | /workspace/coverage/default/17.prim_esc_test.2125426680 | May 23 12:24:25 PM PDT 24 | May 23 12:24:26 PM PDT 24 | 5020286 ps | ||
| T18 | /workspace/coverage/default/19.prim_esc_test.1803522785 | May 23 12:24:19 PM PDT 24 | May 23 12:24:21 PM PDT 24 | 4300083 ps | ||
| T19 | /workspace/coverage/default/14.prim_esc_test.2708589128 | May 23 12:25:46 PM PDT 24 | May 23 12:25:49 PM PDT 24 | 4927964 ps | ||
| T5 | /workspace/coverage/default/3.prim_esc_test.575259695 | May 23 12:25:11 PM PDT 24 | May 23 12:25:12 PM PDT 24 | 5005348 ps | ||
| T20 | /workspace/coverage/default/15.prim_esc_test.438996695 | May 23 12:25:27 PM PDT 24 | May 23 12:25:28 PM PDT 24 | 4812073 ps |
| Test location | /workspace/coverage/default/8.prim_esc_test.3048205449 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5397208 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:25:34 PM PDT 24 |
| Finished | May 23 12:25:36 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-457cf161-3f87-4cb4-807a-1df873d8c188 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048205449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3048205449 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2734800550 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4576007 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:25:09 PM PDT 24 |
| Finished | May 23 12:25:11 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-f6cfd1d8-a198-4c47-b74b-c3a6d0c17d49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734800550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2734800550 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2125426680 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5020286 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:24:25 PM PDT 24 |
| Finished | May 23 12:24:26 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-d0c9a169-82b6-42d8-9a9a-6e92ee250f5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125426680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2125426680 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.575259695 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5005348 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:25:11 PM PDT 24 |
| Finished | May 23 12:25:12 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-e4e8003c-50e7-499c-8dc3-d59c9f519c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575259695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.575259695 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3498117757 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5453062 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:24:02 PM PDT 24 |
| Finished | May 23 12:24:03 PM PDT 24 |
| Peak memory | 146088 kb |
| Host | smart-946dc4ce-bb1b-4940-9f6f-d9507d51c122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498117757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3498117757 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3986880062 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4409624 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:25:34 PM PDT 24 |
| Finished | May 23 12:25:35 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-fdb9b832-01ec-4a49-ac43-71613ca534fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986880062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3986880062 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1697895630 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5229632 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:23:50 PM PDT 24 |
| Finished | May 23 12:23:51 PM PDT 24 |
| Peak memory | 146088 kb |
| Host | smart-260758d8-97e5-4561-80c0-61210711c7c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697895630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1697895630 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2601411611 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4831698 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:23:46 PM PDT 24 |
| Finished | May 23 12:23:47 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-ce30b9f8-6981-4851-8a20-102213c00a14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601411611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2601411611 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.4171078370 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5260718 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:25:21 PM PDT 24 |
| Finished | May 23 12:25:23 PM PDT 24 |
| Peak memory | 146240 kb |
| Host | smart-daffb798-0245-430b-83a9-d5259b19bef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171078370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4171078370 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1882719429 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5012132 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:22:00 PM PDT 24 |
| Finished | May 23 12:22:02 PM PDT 24 |
| Peak memory | 146064 kb |
| Host | smart-96179457-c14a-419b-80df-df5813a9f5d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882719429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1882719429 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.633525756 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4648327 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:26:44 PM PDT 24 |
| Finished | May 23 12:26:48 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-1f3a2644-1968-4830-899a-417ef62e830c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633525756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.633525756 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2708589128 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4927964 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:25:46 PM PDT 24 |
| Finished | May 23 12:25:49 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-0e3a0799-de9f-46fb-94de-738acda8e1f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708589128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2708589128 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.438996695 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4812073 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:25:27 PM PDT 24 |
| Finished | May 23 12:25:28 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-04229aeb-63cc-4063-acf8-c3e233aa1d7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438996695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.438996695 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2629389800 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5118808 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:26:18 PM PDT 24 |
| Finished | May 23 12:26:20 PM PDT 24 |
| Peak memory | 146772 kb |
| Host | smart-e7af0025-8103-414a-82c9-9a1cf6ad309a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629389800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2629389800 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.884719664 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5258784 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:25:50 PM PDT 24 |
| Finished | May 23 12:25:52 PM PDT 24 |
| Peak memory | 146768 kb |
| Host | smart-8bfbffe8-50bd-40bd-8b0d-869ac667930e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884719664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.884719664 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1803522785 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4300083 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:24:19 PM PDT 24 |
| Finished | May 23 12:24:21 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-32566c09-02ef-4b23-8a78-d1e0bd6be32d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803522785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1803522785 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3167236025 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4639466 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:23:18 PM PDT 24 |
| Finished | May 23 12:23:20 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-a72272f7-5c66-43c2-9170-c3af30222d4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167236025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3167236025 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1777154550 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4360694 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:24:04 PM PDT 24 |
| Finished | May 23 12:24:06 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-d22441ea-cffb-467e-bfdb-92bb5bb7b7fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777154550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1777154550 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1627570702 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5349157 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:25:21 PM PDT 24 |
| Finished | May 23 12:25:22 PM PDT 24 |
| Peak memory | 146588 kb |
| Host | smart-5b1c755e-bf7c-4e36-9d30-cf92a7597cd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627570702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1627570702 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.237586563 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5156069 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:24:01 PM PDT 24 |
| Finished | May 23 12:24:03 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-c4511b71-8f10-4928-ae06-6b2d7350a549 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237586563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.237586563 |
| Directory | /workspace/7.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |