| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.01 | 94.29 | 85.37 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.53 | 86.53 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.1494749428 |
| 88.27 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.688306028 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2885931728 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3409662630 |
| /workspace/coverage/default/1.prim_esc_test.4056804623 |
| /workspace/coverage/default/10.prim_esc_test.3223486570 |
| /workspace/coverage/default/11.prim_esc_test.2012607219 |
| /workspace/coverage/default/15.prim_esc_test.3320122709 |
| /workspace/coverage/default/16.prim_esc_test.3983771380 |
| /workspace/coverage/default/17.prim_esc_test.2970200497 |
| /workspace/coverage/default/18.prim_esc_test.3090069970 |
| /workspace/coverage/default/19.prim_esc_test.792252742 |
| /workspace/coverage/default/2.prim_esc_test.3165904097 |
| /workspace/coverage/default/3.prim_esc_test.45974100 |
| /workspace/coverage/default/4.prim_esc_test.3518244800 |
| /workspace/coverage/default/5.prim_esc_test.284555871 |
| /workspace/coverage/default/6.prim_esc_test.3196825115 |
| /workspace/coverage/default/7.prim_esc_test.217263738 |
| /workspace/coverage/default/8.prim_esc_test.2181337099 |
| /workspace/coverage/default/9.prim_esc_test.2462994520 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_esc_test.3090069970 | May 26 01:54:16 PM PDT 24 | May 26 01:54:18 PM PDT 24 | 5048807 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.217263738 | May 26 01:54:12 PM PDT 24 | May 26 01:54:14 PM PDT 24 | 4590249 ps | ||
| T3 | /workspace/coverage/default/1.prim_esc_test.4056804623 | May 26 01:54:07 PM PDT 24 | May 26 01:54:10 PM PDT 24 | 5059657 ps | ||
| T4 | /workspace/coverage/default/10.prim_esc_test.3223486570 | May 26 01:54:14 PM PDT 24 | May 26 01:54:15 PM PDT 24 | 4947227 ps | ||
| T5 | /workspace/coverage/default/12.prim_esc_test.1494749428 | May 26 01:54:10 PM PDT 24 | May 26 01:54:13 PM PDT 24 | 5360181 ps | ||
| T11 | /workspace/coverage/default/17.prim_esc_test.2970200497 | May 26 01:54:09 PM PDT 24 | May 26 01:54:11 PM PDT 24 | 4255046 ps | ||
| T6 | /workspace/coverage/default/0.prim_esc_test.3409662630 | May 26 01:54:15 PM PDT 24 | May 26 01:54:16 PM PDT 24 | 4706035 ps | ||
| T12 | /workspace/coverage/default/2.prim_esc_test.3165904097 | May 26 01:54:11 PM PDT 24 | May 26 01:54:14 PM PDT 24 | 4314765 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.2012607219 | May 26 01:54:15 PM PDT 24 | May 26 01:54:16 PM PDT 24 | 5131561 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.3320122709 | May 26 01:54:09 PM PDT 24 | May 26 01:54:11 PM PDT 24 | 5077750 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.45974100 | May 26 01:54:12 PM PDT 24 | May 26 01:54:14 PM PDT 24 | 5006613 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.3983771380 | May 26 01:54:12 PM PDT 24 | May 26 01:54:14 PM PDT 24 | 4829145 ps | ||
| T8 | /workspace/coverage/default/13.prim_esc_test.688306028 | May 26 01:54:07 PM PDT 24 | May 26 01:54:10 PM PDT 24 | 4824985 ps | ||
| T10 | /workspace/coverage/default/14.prim_esc_test.2885931728 | May 26 01:54:08 PM PDT 24 | May 26 01:54:10 PM PDT 24 | 4746686 ps | ||
| T13 | /workspace/coverage/default/6.prim_esc_test.3196825115 | May 26 01:54:09 PM PDT 24 | May 26 01:54:11 PM PDT 24 | 4724833 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.3518244800 | May 26 01:54:12 PM PDT 24 | May 26 01:54:14 PM PDT 24 | 4804699 ps | ||
| T17 | /workspace/coverage/default/5.prim_esc_test.284555871 | May 26 01:54:11 PM PDT 24 | May 26 01:54:14 PM PDT 24 | 4533387 ps | ||
| T18 | /workspace/coverage/default/8.prim_esc_test.2181337099 | May 26 01:54:11 PM PDT 24 | May 26 01:54:13 PM PDT 24 | 5251458 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.792252742 | May 26 01:54:22 PM PDT 24 | May 26 01:54:23 PM PDT 24 | 4944892 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.2462994520 | May 26 01:54:08 PM PDT 24 | May 26 01:54:11 PM PDT 24 | 4804951 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.1494749428 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5360181 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:54:13 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-d8c6d13d-d6ad-46d2-84ee-8e9fd5d0d6b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494749428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1494749428 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.688306028 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4824985 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:54:10 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-b07ed8e0-54b6-4f90-bfbb-4e1f35e998ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688306028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.688306028 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2885931728 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4746686 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:54:10 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-0c3e6ad8-8423-49b4-85d4-720d975c65a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885931728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2885931728 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3409662630 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4706035 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:16 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-16126918-cfd4-4df5-90e8-fe8b747d519d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409662630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3409662630 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4056804623 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5059657 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:54:10 PM PDT 24 |
| Peak memory | 146088 kb |
| Host | smart-e502d967-2ac7-4ca4-8bc8-6ba75c722c29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056804623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4056804623 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3223486570 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4947227 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:14 PM PDT 24 |
| Finished | May 26 01:54:15 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-2e44c122-38f4-407a-bf34-9481b0bbc81f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223486570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3223486570 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2012607219 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5131561 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:16 PM PDT 24 |
| Peak memory | 146264 kb |
| Host | smart-4c98cce3-43a2-46f9-b5ae-f6c2709e1ce4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012607219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2012607219 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3320122709 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5077750 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:54:11 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-588924de-044b-4492-98d2-23f31b54a140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320122709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3320122709 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3983771380 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4829145 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 146156 kb |
| Host | smart-2ad337e4-7f05-49d9-95fa-7c29924ea991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983771380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3983771380 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2970200497 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4255046 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:54:11 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-184844b6-35d0-4185-b46e-ef5bc3bc9572 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970200497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2970200497 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3090069970 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5048807 ps |
| CPU time | 0.45 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:18 PM PDT 24 |
| Peak memory | 146172 kb |
| Host | smart-abf790fe-2259-43cc-93d1-01bb85a8eb84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090069970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3090069970 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.792252742 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4944892 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:22 PM PDT 24 |
| Finished | May 26 01:54:23 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-e1ac4998-cce9-49ab-84c6-fdbffd7a7faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792252742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.792252742 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3165904097 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4314765 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-d258102c-d5eb-467b-a559-660a0ebe94ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165904097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3165904097 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.45974100 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5006613 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-52a9767f-cee0-40ce-8057-bb4362e75107 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45974100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.45974100 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3518244800 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4804699 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-2b53b096-15ee-4040-be19-458275ebb82f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518244800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3518244800 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.284555871 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4533387 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-173eb13c-429c-44a3-a268-3b705fd199d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284555871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.284555871 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3196825115 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4724833 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:54:11 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-9582d080-f186-4c9b-8621-b8226fb1757b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196825115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3196825115 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.217263738 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4590249 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-db5b8a70-920a-4893-b51f-846e970939c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217263738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.217263738 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2181337099 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5251458 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:13 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-6a1090f6-ded2-4190-910e-a55de32f0db9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181337099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2181337099 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2462994520 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4804951 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:54:11 PM PDT 24 |
| Peak memory | 146124 kb |
| Host | smart-e801f314-25cd-4594-9b69-f848a62aca04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462994520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2462994520 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |