| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.3292497188 |
| 88.27 | 2.74 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.4159618723 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3146615624 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.729789153 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2377342789 |
| /workspace/coverage/default/1.prim_esc_test.191488433 |
| /workspace/coverage/default/11.prim_esc_test.3215798338 |
| /workspace/coverage/default/13.prim_esc_test.1183393704 |
| /workspace/coverage/default/14.prim_esc_test.1842663376 |
| /workspace/coverage/default/16.prim_esc_test.78507952 |
| /workspace/coverage/default/17.prim_esc_test.4282561278 |
| /workspace/coverage/default/18.prim_esc_test.1822101498 |
| /workspace/coverage/default/19.prim_esc_test.3199421852 |
| /workspace/coverage/default/2.prim_esc_test.1605132150 |
| /workspace/coverage/default/3.prim_esc_test.2725965353 |
| /workspace/coverage/default/4.prim_esc_test.3458951507 |
| /workspace/coverage/default/5.prim_esc_test.3676629644 |
| /workspace/coverage/default/6.prim_esc_test.436964007 |
| /workspace/coverage/default/7.prim_esc_test.399069823 |
| /workspace/coverage/default/8.prim_esc_test.1572702411 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_esc_test.3199421852 | May 28 12:48:33 PM PDT 24 | May 28 12:48:35 PM PDT 24 | 4572637 ps | ||
| T2 | /workspace/coverage/default/3.prim_esc_test.2725965353 | May 28 12:43:03 PM PDT 24 | May 28 12:43:05 PM PDT 24 | 4692918 ps | ||
| T3 | /workspace/coverage/default/6.prim_esc_test.436964007 | May 28 12:43:09 PM PDT 24 | May 28 12:43:10 PM PDT 24 | 5132042 ps | ||
| T7 | /workspace/coverage/default/14.prim_esc_test.1842663376 | May 28 12:48:18 PM PDT 24 | May 28 12:48:19 PM PDT 24 | 5029879 ps | ||
| T4 | /workspace/coverage/default/4.prim_esc_test.3458951507 | May 28 12:43:10 PM PDT 24 | May 28 12:43:11 PM PDT 24 | 4732733 ps | ||
| T6 | /workspace/coverage/default/12.prim_esc_test.3292497188 | May 28 12:48:17 PM PDT 24 | May 28 12:48:18 PM PDT 24 | 4939475 ps | ||
| T12 | /workspace/coverage/default/13.prim_esc_test.1183393704 | May 28 12:44:49 PM PDT 24 | May 28 12:44:50 PM PDT 24 | 5003480 ps | ||
| T5 | /workspace/coverage/default/7.prim_esc_test.399069823 | May 28 12:43:09 PM PDT 24 | May 28 12:43:10 PM PDT 24 | 4920091 ps | ||
| T8 | /workspace/coverage/default/9.prim_esc_test.4159618723 | May 28 12:43:09 PM PDT 24 | May 28 12:43:11 PM PDT 24 | 4204830 ps | ||
| T15 | /workspace/coverage/default/18.prim_esc_test.1822101498 | May 28 12:48:34 PM PDT 24 | May 28 12:48:35 PM PDT 24 | 5101968 ps | ||
| T9 | /workspace/coverage/default/8.prim_esc_test.1572702411 | May 28 12:43:09 PM PDT 24 | May 28 12:43:10 PM PDT 24 | 5182432 ps | ||
| T17 | /workspace/coverage/default/5.prim_esc_test.3676629644 | May 28 12:43:09 PM PDT 24 | May 28 12:43:11 PM PDT 24 | 5014159 ps | ||
| T10 | /workspace/coverage/default/15.prim_esc_test.3146615624 | May 28 12:48:30 PM PDT 24 | May 28 12:48:31 PM PDT 24 | 4889285 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.78507952 | May 28 12:46:33 PM PDT 24 | May 28 12:46:34 PM PDT 24 | 4882522 ps | ||
| T19 | /workspace/coverage/default/2.prim_esc_test.1605132150 | May 28 12:43:09 PM PDT 24 | May 28 12:43:10 PM PDT 24 | 4948321 ps | ||
| T13 | /workspace/coverage/default/11.prim_esc_test.3215798338 | May 28 12:46:44 PM PDT 24 | May 28 12:46:45 PM PDT 24 | 5199982 ps | ||
| T11 | /workspace/coverage/default/0.prim_esc_test.2377342789 | May 28 12:43:10 PM PDT 24 | May 28 12:43:11 PM PDT 24 | 4783282 ps | ||
| T14 | /workspace/coverage/default/10.prim_esc_test.729789153 | May 28 12:48:18 PM PDT 24 | May 28 12:48:19 PM PDT 24 | 4952458 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.4282561278 | May 28 12:49:00 PM PDT 24 | May 28 12:49:01 PM PDT 24 | 4815097 ps | ||
| T16 | /workspace/coverage/default/1.prim_esc_test.191488433 | May 28 12:43:10 PM PDT 24 | May 28 12:43:11 PM PDT 24 | 4933472 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.3292497188 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4939475 ps |
| CPU time | 0.39 seconds |
| Started | May 28 12:48:17 PM PDT 24 |
| Finished | May 28 12:48:18 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-0fcd81f2-893a-45d4-83c3-c558dac543b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292497188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3292497188 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.4159618723 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4204830 ps |
| CPU time | 0.41 seconds |
| Started | May 28 12:43:09 PM PDT 24 |
| Finished | May 28 12:43:11 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-415de9fb-0b80-4a75-8d8f-594037af23dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159618723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4159618723 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3146615624 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4889285 ps |
| CPU time | 0.4 seconds |
| Started | May 28 12:48:30 PM PDT 24 |
| Finished | May 28 12:48:31 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-282cf6db-8872-47e4-bcde-92686264f0d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146615624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3146615624 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.729789153 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4952458 ps |
| CPU time | 0.36 seconds |
| Started | May 28 12:48:18 PM PDT 24 |
| Finished | May 28 12:48:19 PM PDT 24 |
| Peak memory | 146648 kb |
| Host | smart-4141a966-3ed3-4fc6-a613-76383ff23235 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729789153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.729789153 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2377342789 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4783282 ps |
| CPU time | 0.41 seconds |
| Started | May 28 12:43:10 PM PDT 24 |
| Finished | May 28 12:43:11 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-1459ee18-117d-49e9-9ca5-6c93bf9ea695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377342789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2377342789 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.191488433 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4933472 ps |
| CPU time | 0.4 seconds |
| Started | May 28 12:43:10 PM PDT 24 |
| Finished | May 28 12:43:11 PM PDT 24 |
| Peak memory | 146316 kb |
| Host | smart-84c3934f-fafa-460f-9f1f-2da452642fc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191488433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.191488433 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3215798338 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5199982 ps |
| CPU time | 0.4 seconds |
| Started | May 28 12:46:44 PM PDT 24 |
| Finished | May 28 12:46:45 PM PDT 24 |
| Peak memory | 146328 kb |
| Host | smart-76e5f7dc-7e62-4208-a906-0ba3e369d5e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215798338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3215798338 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1183393704 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5003480 ps |
| CPU time | 0.42 seconds |
| Started | May 28 12:44:49 PM PDT 24 |
| Finished | May 28 12:44:50 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-197dccd4-cc3d-4661-b9be-c6f83cde15ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183393704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1183393704 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1842663376 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5029879 ps |
| CPU time | 0.36 seconds |
| Started | May 28 12:48:18 PM PDT 24 |
| Finished | May 28 12:48:19 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-688c3780-50ff-45e1-80ff-0802ea019731 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842663376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1842663376 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.78507952 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4882522 ps |
| CPU time | 0.39 seconds |
| Started | May 28 12:46:33 PM PDT 24 |
| Finished | May 28 12:46:34 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-79b232f5-1695-4d65-b91e-985d9276ee19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78507952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.78507952 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.4282561278 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4815097 ps |
| CPU time | 0.41 seconds |
| Started | May 28 12:49:00 PM PDT 24 |
| Finished | May 28 12:49:01 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-45e082ce-4291-47cf-9079-8ad54c19ef9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282561278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.4282561278 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1822101498 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5101968 ps |
| CPU time | 0.37 seconds |
| Started | May 28 12:48:34 PM PDT 24 |
| Finished | May 28 12:48:35 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-ae92c76a-93db-41d3-b3e4-e7a051c22448 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822101498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1822101498 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3199421852 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4572637 ps |
| CPU time | 0.45 seconds |
| Started | May 28 12:48:33 PM PDT 24 |
| Finished | May 28 12:48:35 PM PDT 24 |
| Peak memory | 146408 kb |
| Host | smart-55a34479-2299-42e9-9773-d44e93c82fd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199421852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3199421852 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1605132150 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4948321 ps |
| CPU time | 0.45 seconds |
| Started | May 28 12:43:09 PM PDT 24 |
| Finished | May 28 12:43:10 PM PDT 24 |
| Peak memory | 144392 kb |
| Host | smart-f2323875-8506-4437-8e8f-6c25c1a1c611 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605132150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1605132150 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2725965353 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4692918 ps |
| CPU time | 0.47 seconds |
| Started | May 28 12:43:03 PM PDT 24 |
| Finished | May 28 12:43:05 PM PDT 24 |
| Peak memory | 146452 kb |
| Host | smart-f41adc22-5205-4f93-976f-498e7e760ef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725965353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2725965353 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3458951507 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4732733 ps |
| CPU time | 0.39 seconds |
| Started | May 28 12:43:10 PM PDT 24 |
| Finished | May 28 12:43:11 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-52c8c1e0-c33e-4259-ad38-cb990579925c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458951507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3458951507 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3676629644 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5014159 ps |
| CPU time | 0.39 seconds |
| Started | May 28 12:43:09 PM PDT 24 |
| Finished | May 28 12:43:11 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-e1e4a204-4923-4c4a-ae9b-a89726d602c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676629644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3676629644 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.436964007 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5132042 ps |
| CPU time | 0.46 seconds |
| Started | May 28 12:43:09 PM PDT 24 |
| Finished | May 28 12:43:10 PM PDT 24 |
| Peak memory | 144228 kb |
| Host | smart-a3b9d517-d537-4245-b94c-b7f499b1a112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436964007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.436964007 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.399069823 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4920091 ps |
| CPU time | 0.46 seconds |
| Started | May 28 12:43:09 PM PDT 24 |
| Finished | May 28 12:43:10 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-a3662b05-bcb4-4472-a5fd-06f712e61edf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399069823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.399069823 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1572702411 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5182432 ps |
| CPU time | 0.45 seconds |
| Started | May 28 12:43:09 PM PDT 24 |
| Finished | May 28 12:43:10 PM PDT 24 |
| Peak memory | 143972 kb |
| Host | smart-4456cbb3-a353-404a-9593-efd71735a73a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572702411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1572702411 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |