| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.53 | 86.53 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/9.prim_esc_test.756345032 |
| 88.27 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.3139712318 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1840405701 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.1261810436 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1555819772 |
| /workspace/coverage/default/10.prim_esc_test.995597287 |
| /workspace/coverage/default/11.prim_esc_test.737137921 |
| /workspace/coverage/default/13.prim_esc_test.1219983901 |
| /workspace/coverage/default/15.prim_esc_test.1494459415 |
| /workspace/coverage/default/16.prim_esc_test.1786967225 |
| /workspace/coverage/default/17.prim_esc_test.288581112 |
| /workspace/coverage/default/18.prim_esc_test.1967576475 |
| /workspace/coverage/default/19.prim_esc_test.2753755079 |
| /workspace/coverage/default/2.prim_esc_test.1334040535 |
| /workspace/coverage/default/3.prim_esc_test.2780715062 |
| /workspace/coverage/default/4.prim_esc_test.1780839274 |
| /workspace/coverage/default/5.prim_esc_test.2092968701 |
| /workspace/coverage/default/6.prim_esc_test.1622916480 |
| /workspace/coverage/default/7.prim_esc_test.884884283 |
| /workspace/coverage/default/8.prim_esc_test.3776652522 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_esc_test.995597287 | May 30 02:05:42 PM PDT 24 | May 30 02:05:43 PM PDT 24 | 4905992 ps | ||
| T2 | /workspace/coverage/default/9.prim_esc_test.756345032 | May 30 02:05:39 PM PDT 24 | May 30 02:05:41 PM PDT 24 | 5074395 ps | ||
| T3 | /workspace/coverage/default/6.prim_esc_test.1622916480 | May 30 02:05:39 PM PDT 24 | May 30 02:05:41 PM PDT 24 | 4929117 ps | ||
| T8 | /workspace/coverage/default/7.prim_esc_test.884884283 | May 30 02:05:40 PM PDT 24 | May 30 02:05:42 PM PDT 24 | 4549035 ps | ||
| T4 | /workspace/coverage/default/1.prim_esc_test.3139712318 | May 30 02:05:41 PM PDT 24 | May 30 02:05:43 PM PDT 24 | 4652122 ps | ||
| T15 | /workspace/coverage/default/2.prim_esc_test.1334040535 | May 30 02:05:43 PM PDT 24 | May 30 02:05:45 PM PDT 24 | 5079007 ps | ||
| T16 | /workspace/coverage/default/19.prim_esc_test.2753755079 | May 30 02:05:42 PM PDT 24 | May 30 02:05:44 PM PDT 24 | 4403670 ps | ||
| T17 | /workspace/coverage/default/4.prim_esc_test.1780839274 | May 30 02:05:48 PM PDT 24 | May 30 02:05:49 PM PDT 24 | 4651509 ps | ||
| T9 | /workspace/coverage/default/17.prim_esc_test.288581112 | May 30 02:05:43 PM PDT 24 | May 30 02:05:45 PM PDT 24 | 5219788 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.1261810436 | May 30 02:05:45 PM PDT 24 | May 30 02:05:46 PM PDT 24 | 4844456 ps | ||
| T12 | /workspace/coverage/default/11.prim_esc_test.737137921 | May 30 02:05:46 PM PDT 24 | May 30 02:05:47 PM PDT 24 | 5270477 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.1786967225 | May 30 02:05:43 PM PDT 24 | May 30 02:05:45 PM PDT 24 | 4773832 ps | ||
| T5 | /workspace/coverage/default/13.prim_esc_test.1219983901 | May 30 02:05:43 PM PDT 24 | May 30 02:05:44 PM PDT 24 | 5382260 ps | ||
| T6 | /workspace/coverage/default/15.prim_esc_test.1494459415 | May 30 02:05:40 PM PDT 24 | May 30 02:05:42 PM PDT 24 | 4564788 ps | ||
| T19 | /workspace/coverage/default/0.prim_esc_test.1555819772 | May 30 02:05:40 PM PDT 24 | May 30 02:05:42 PM PDT 24 | 4169661 ps | ||
| T20 | /workspace/coverage/default/8.prim_esc_test.3776652522 | May 30 02:05:40 PM PDT 24 | May 30 02:05:42 PM PDT 24 | 4902784 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.2780715062 | May 30 02:05:44 PM PDT 24 | May 30 02:05:46 PM PDT 24 | 4475090 ps | ||
| T10 | /workspace/coverage/default/14.prim_esc_test.1840405701 | May 30 02:05:43 PM PDT 24 | May 30 02:05:45 PM PDT 24 | 4760795 ps | ||
| T7 | /workspace/coverage/default/18.prim_esc_test.1967576475 | May 30 02:05:37 PM PDT 24 | May 30 02:05:38 PM PDT 24 | 5419115 ps | ||
| T14 | /workspace/coverage/default/5.prim_esc_test.2092968701 | May 30 02:05:40 PM PDT 24 | May 30 02:05:42 PM PDT 24 | 5215373 ps |
| Test location | /workspace/coverage/default/9.prim_esc_test.756345032 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5074395 ps |
| CPU time | 0.37 seconds |
| Started | May 30 02:05:39 PM PDT 24 |
| Finished | May 30 02:05:41 PM PDT 24 |
| Peak memory | 146184 kb |
| Host | smart-03dc401e-c17e-4244-8378-a2c222cb5b59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756345032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.756345032 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3139712318 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4652122 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:41 PM PDT 24 |
| Finished | May 30 02:05:43 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-9b5605ea-8e6e-407c-aeee-ba0bd5896241 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139712318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3139712318 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1840405701 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4760795 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:43 PM PDT 24 |
| Finished | May 30 02:05:45 PM PDT 24 |
| Peak memory | 146212 kb |
| Host | smart-22b706a9-9088-4f02-b17f-60a077c9f0bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840405701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1840405701 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1261810436 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4844456 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:45 PM PDT 24 |
| Finished | May 30 02:05:46 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-7052c54c-e696-44f4-9552-94e0aa27b248 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261810436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1261810436 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1555819772 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4169661 ps |
| CPU time | 0.37 seconds |
| Started | May 30 02:05:40 PM PDT 24 |
| Finished | May 30 02:05:42 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-020c0a6c-6cde-4453-befd-0b0da7c025b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555819772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1555819772 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.995597287 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4905992 ps |
| CPU time | 0.36 seconds |
| Started | May 30 02:05:42 PM PDT 24 |
| Finished | May 30 02:05:43 PM PDT 24 |
| Peak memory | 146200 kb |
| Host | smart-ddd57054-2768-4198-92ce-d90c3cfe58d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995597287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.995597287 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.737137921 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5270477 ps |
| CPU time | 0.41 seconds |
| Started | May 30 02:05:46 PM PDT 24 |
| Finished | May 30 02:05:47 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-992930b2-7c85-4e0c-9e87-41a045462bc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737137921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.737137921 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1219983901 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5382260 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:43 PM PDT 24 |
| Finished | May 30 02:05:44 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-561474e3-20a7-46ae-b160-fd8102077125 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219983901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1219983901 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1494459415 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4564788 ps |
| CPU time | 0.37 seconds |
| Started | May 30 02:05:40 PM PDT 24 |
| Finished | May 30 02:05:42 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-f305b47b-7178-4135-8e32-104c35ffc572 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494459415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1494459415 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1786967225 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4773832 ps |
| CPU time | 0.39 seconds |
| Started | May 30 02:05:43 PM PDT 24 |
| Finished | May 30 02:05:45 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-e1e6b53f-0c1d-4527-b34e-74efac64c132 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786967225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1786967225 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.288581112 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5219788 ps |
| CPU time | 0.39 seconds |
| Started | May 30 02:05:43 PM PDT 24 |
| Finished | May 30 02:05:45 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-0168da81-2db3-4d97-96ca-3a3ab61181b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288581112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.288581112 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1967576475 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5419115 ps |
| CPU time | 0.36 seconds |
| Started | May 30 02:05:37 PM PDT 24 |
| Finished | May 30 02:05:38 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-d1ada92c-ca78-4b6d-b3a9-f6f58fa3d570 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967576475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1967576475 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2753755079 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4403670 ps |
| CPU time | 0.37 seconds |
| Started | May 30 02:05:42 PM PDT 24 |
| Finished | May 30 02:05:44 PM PDT 24 |
| Peak memory | 146212 kb |
| Host | smart-b99223fe-5e38-484a-a23c-28d952c7b375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753755079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2753755079 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1334040535 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5079007 ps |
| CPU time | 0.39 seconds |
| Started | May 30 02:05:43 PM PDT 24 |
| Finished | May 30 02:05:45 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-a8c54339-54ab-49be-ba45-a372ecfcd68d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334040535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1334040535 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2780715062 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4475090 ps |
| CPU time | 0.47 seconds |
| Started | May 30 02:05:44 PM PDT 24 |
| Finished | May 30 02:05:46 PM PDT 24 |
| Peak memory | 146124 kb |
| Host | smart-4f9bb45b-a33c-4a49-8161-a06fec742382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780715062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2780715062 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1780839274 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4651509 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:48 PM PDT 24 |
| Finished | May 30 02:05:49 PM PDT 24 |
| Peak memory | 146108 kb |
| Host | smart-b478c13b-5f53-4fb0-9469-7cdca3a74499 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780839274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1780839274 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2092968701 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5215373 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:40 PM PDT 24 |
| Finished | May 30 02:05:42 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-1657a7fd-a409-42af-83d5-f86d9f494e38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092968701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2092968701 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1622916480 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4929117 ps |
| CPU time | 0.38 seconds |
| Started | May 30 02:05:39 PM PDT 24 |
| Finished | May 30 02:05:41 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-bc58974d-a1f6-4190-a8c8-874df5148a1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622916480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1622916480 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.884884283 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4549035 ps |
| CPU time | 0.37 seconds |
| Started | May 30 02:05:40 PM PDT 24 |
| Finished | May 30 02:05:42 PM PDT 24 |
| Peak memory | 146200 kb |
| Host | smart-704b623f-fbef-4126-89b6-b3c50e252995 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884884283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.884884283 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3776652522 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4902784 ps |
| CPU time | 0.4 seconds |
| Started | May 30 02:05:40 PM PDT 24 |
| Finished | May 30 02:05:42 PM PDT 24 |
| Peak memory | 146148 kb |
| Host | smart-334b9923-be0c-47ac-9818-c8342e513d88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776652522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3776652522 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |