Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.53 86.53 92.38 92.38 85.37 85.37 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/12.prim_esc_test.4097439903
88.27 1.74 93.33 0.95 85.37 0.00 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.1998593036
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.1034758067
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/14.prim_esc_test.875619434

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.1572566502
/workspace/coverage/default/1.prim_esc_test.3478006959
/workspace/coverage/default/10.prim_esc_test.2936402956
/workspace/coverage/default/11.prim_esc_test.2171280930
/workspace/coverage/default/13.prim_esc_test.3469343174
/workspace/coverage/default/16.prim_esc_test.3317777205
/workspace/coverage/default/17.prim_esc_test.311011319
/workspace/coverage/default/18.prim_esc_test.1531151535
/workspace/coverage/default/2.prim_esc_test.520923762
/workspace/coverage/default/3.prim_esc_test.4119531178
/workspace/coverage/default/4.prim_esc_test.879852189
/workspace/coverage/default/5.prim_esc_test.2786304689
/workspace/coverage/default/6.prim_esc_test.1864504379
/workspace/coverage/default/7.prim_esc_test.3117856191
/workspace/coverage/default/8.prim_esc_test.4060805761
/workspace/coverage/default/9.prim_esc_test.3764903805



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_esc_test.4097439903 Jun 02 02:03:04 PM PDT 24 Jun 02 02:03:05 PM PDT 24 4943436 ps
T2 /workspace/coverage/default/19.prim_esc_test.1034758067 Jun 02 02:03:02 PM PDT 24 Jun 02 02:03:03 PM PDT 24 4678210 ps
T3 /workspace/coverage/default/13.prim_esc_test.3469343174 Jun 02 02:03:04 PM PDT 24 Jun 02 02:03:05 PM PDT 24 4882626 ps
T5 /workspace/coverage/default/16.prim_esc_test.3317777205 Jun 02 02:03:03 PM PDT 24 Jun 02 02:03:04 PM PDT 24 4601172 ps
T14 /workspace/coverage/default/1.prim_esc_test.3478006959 Jun 02 02:02:58 PM PDT 24 Jun 02 02:02:59 PM PDT 24 4867289 ps
T4 /workspace/coverage/default/6.prim_esc_test.1864504379 Jun 02 02:03:06 PM PDT 24 Jun 02 02:03:06 PM PDT 24 3972080 ps
T10 /workspace/coverage/default/7.prim_esc_test.3117856191 Jun 02 02:03:03 PM PDT 24 Jun 02 02:03:04 PM PDT 24 4605952 ps
T15 /workspace/coverage/default/3.prim_esc_test.4119531178 Jun 02 02:02:59 PM PDT 24 Jun 02 02:03:00 PM PDT 24 5197967 ps
T7 /workspace/coverage/default/11.prim_esc_test.2171280930 Jun 02 02:03:03 PM PDT 24 Jun 02 02:03:04 PM PDT 24 4831485 ps
T16 /workspace/coverage/default/18.prim_esc_test.1531151535 Jun 02 02:03:05 PM PDT 24 Jun 02 02:03:06 PM PDT 24 4956384 ps
T12 /workspace/coverage/default/8.prim_esc_test.4060805761 Jun 02 02:03:04 PM PDT 24 Jun 02 02:03:05 PM PDT 24 5293440 ps
T17 /workspace/coverage/default/9.prim_esc_test.3764903805 Jun 02 02:03:06 PM PDT 24 Jun 02 02:03:06 PM PDT 24 4611416 ps
T18 /workspace/coverage/default/0.prim_esc_test.1572566502 Jun 02 02:02:57 PM PDT 24 Jun 02 02:02:58 PM PDT 24 5101654 ps
T6 /workspace/coverage/default/14.prim_esc_test.875619434 Jun 02 02:03:02 PM PDT 24 Jun 02 02:03:03 PM PDT 24 4715038 ps
T8 /workspace/coverage/default/5.prim_esc_test.2786304689 Jun 02 02:02:59 PM PDT 24 Jun 02 02:02:59 PM PDT 24 4769647 ps
T11 /workspace/coverage/default/17.prim_esc_test.311011319 Jun 02 02:03:03 PM PDT 24 Jun 02 02:03:04 PM PDT 24 5487838 ps
T13 /workspace/coverage/default/10.prim_esc_test.2936402956 Jun 02 02:03:02 PM PDT 24 Jun 02 02:03:02 PM PDT 24 3978125 ps
T19 /workspace/coverage/default/4.prim_esc_test.879852189 Jun 02 02:02:57 PM PDT 24 Jun 02 02:02:58 PM PDT 24 4675295 ps
T20 /workspace/coverage/default/2.prim_esc_test.520923762 Jun 02 02:02:59 PM PDT 24 Jun 02 02:03:00 PM PDT 24 4286420 ps
T9 /workspace/coverage/default/15.prim_esc_test.1998593036 Jun 02 02:03:05 PM PDT 24 Jun 02 02:03:06 PM PDT 24 4269934 ps

Test location /workspace/coverage/default/12.prim_esc_test.4097439903
Short name T1
Test name
Test status
Simulation time 4943436 ps
CPU time 0.42 seconds
Started Jun 02 02:03:04 PM PDT 24
Finished Jun 02 02:03:05 PM PDT 24
Peak memory 146188 kb
Host smart-bd2f18ec-70d5-4a93-918a-029da6315b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097439903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4097439903
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1998593036
Short name T9
Test name
Test status
Simulation time 4269934 ps
CPU time 0.44 seconds
Started Jun 02 02:03:05 PM PDT 24
Finished Jun 02 02:03:06 PM PDT 24
Peak memory 146092 kb
Host smart-1130ed80-c5d4-45d2-9d28-bb6048e3df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998593036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1998593036
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1034758067
Short name T2
Test name
Test status
Simulation time 4678210 ps
CPU time 0.39 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:03 PM PDT 24
Peak memory 146192 kb
Host smart-8db4f9ae-6453-461a-a291-1f06c9b4f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034758067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1034758067
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.875619434
Short name T6
Test name
Test status
Simulation time 4715038 ps
CPU time 0.41 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:03 PM PDT 24
Peak memory 146128 kb
Host smart-a0eb1736-3871-4d29-8488-768e467b58ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875619434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.875619434
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.1572566502
Short name T18
Test name
Test status
Simulation time 5101654 ps
CPU time 0.4 seconds
Started Jun 02 02:02:57 PM PDT 24
Finished Jun 02 02:02:58 PM PDT 24
Peak memory 146052 kb
Host smart-2491e094-afaa-4009-9a58-311e920d08a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572566502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1572566502
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3478006959
Short name T14
Test name
Test status
Simulation time 4867289 ps
CPU time 0.37 seconds
Started Jun 02 02:02:58 PM PDT 24
Finished Jun 02 02:02:59 PM PDT 24
Peak memory 146044 kb
Host smart-36c29e3f-062c-4ffe-9739-c7cbb1a1e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478006959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3478006959
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2936402956
Short name T13
Test name
Test status
Simulation time 3978125 ps
CPU time 0.39 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:02 PM PDT 24
Peak memory 146180 kb
Host smart-a6618ff2-a6a5-45d1-826d-be4ab6af7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936402956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2936402956
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2171280930
Short name T7
Test name
Test status
Simulation time 4831485 ps
CPU time 0.4 seconds
Started Jun 02 02:03:03 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 146188 kb
Host smart-c71c29fc-bda5-474e-a3f9-6b20f64bda9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171280930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2171280930
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.3469343174
Short name T3
Test name
Test status
Simulation time 4882626 ps
CPU time 0.38 seconds
Started Jun 02 02:03:04 PM PDT 24
Finished Jun 02 02:03:05 PM PDT 24
Peak memory 146164 kb
Host smart-45eb7e9f-e7b1-4416-90fa-84a7e62fa112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469343174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3469343174
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.3317777205
Short name T5
Test name
Test status
Simulation time 4601172 ps
CPU time 0.42 seconds
Started Jun 02 02:03:03 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 146128 kb
Host smart-049ed56b-8954-4e63-96f7-d44d0967136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317777205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3317777205
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.311011319
Short name T11
Test name
Test status
Simulation time 5487838 ps
CPU time 0.4 seconds
Started Jun 02 02:03:03 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 146312 kb
Host smart-986ef062-ca2c-4b22-aaac-fc1367fb95db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311011319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.311011319
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1531151535
Short name T16
Test name
Test status
Simulation time 4956384 ps
CPU time 0.44 seconds
Started Jun 02 02:03:05 PM PDT 24
Finished Jun 02 02:03:06 PM PDT 24
Peak memory 146132 kb
Host smart-e2e2b3ad-1a63-4279-8678-410e32e6525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531151535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1531151535
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.520923762
Short name T20
Test name
Test status
Simulation time 4286420 ps
CPU time 0.39 seconds
Started Jun 02 02:02:59 PM PDT 24
Finished Jun 02 02:03:00 PM PDT 24
Peak memory 146168 kb
Host smart-02b66d9a-c206-4375-9e20-fdffe691bd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520923762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.520923762
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.4119531178
Short name T15
Test name
Test status
Simulation time 5197967 ps
CPU time 0.37 seconds
Started Jun 02 02:02:59 PM PDT 24
Finished Jun 02 02:03:00 PM PDT 24
Peak memory 146088 kb
Host smart-21ef0da0-a7c5-4583-86d1-dece16eb870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119531178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4119531178
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.879852189
Short name T19
Test name
Test status
Simulation time 4675295 ps
CPU time 0.37 seconds
Started Jun 02 02:02:57 PM PDT 24
Finished Jun 02 02:02:58 PM PDT 24
Peak memory 146156 kb
Host smart-fe3cfc56-9cac-448a-a81c-c4298d3188c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879852189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.879852189
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.2786304689
Short name T8
Test name
Test status
Simulation time 4769647 ps
CPU time 0.4 seconds
Started Jun 02 02:02:59 PM PDT 24
Finished Jun 02 02:02:59 PM PDT 24
Peak memory 146100 kb
Host smart-93519c29-427c-4b67-a47d-f2e7589c48d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786304689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2786304689
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1864504379
Short name T4
Test name
Test status
Simulation time 3972080 ps
CPU time 0.4 seconds
Started Jun 02 02:03:06 PM PDT 24
Finished Jun 02 02:03:06 PM PDT 24
Peak memory 146072 kb
Host smart-7aef9476-e597-43cf-b26b-3e7de1466834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864504379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1864504379
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3117856191
Short name T10
Test name
Test status
Simulation time 4605952 ps
CPU time 0.42 seconds
Started Jun 02 02:03:03 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 146044 kb
Host smart-e2d43f31-76e7-4ac9-b14e-b14b0d36bdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117856191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3117856191
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.4060805761
Short name T12
Test name
Test status
Simulation time 5293440 ps
CPU time 0.4 seconds
Started Jun 02 02:03:04 PM PDT 24
Finished Jun 02 02:03:05 PM PDT 24
Peak memory 146052 kb
Host smart-23d85fae-7925-494c-96b5-dee9900240d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060805761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.4060805761
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3764903805
Short name T17
Test name
Test status
Simulation time 4611416 ps
CPU time 0.37 seconds
Started Jun 02 02:03:06 PM PDT 24
Finished Jun 02 02:03:06 PM PDT 24
Peak memory 146056 kb
Host smart-dfa68d51-851d-4614-9c68-1edc87b5765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764903805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3764903805
Directory /workspace/9.prim_esc_test/latest
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