| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/8.prim_esc_test.2493584494 |
| 87.67 | 2.14 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.628995295 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.746014697 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.3786795000 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.3603889948 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.1537601921 |
| /workspace/coverage/default/10.prim_esc_test.3395923187 |
| /workspace/coverage/default/11.prim_esc_test.3360312023 |
| /workspace/coverage/default/13.prim_esc_test.75345682 |
| /workspace/coverage/default/15.prim_esc_test.4175985508 |
| /workspace/coverage/default/16.prim_esc_test.2912260913 |
| /workspace/coverage/default/17.prim_esc_test.3289331483 |
| /workspace/coverage/default/18.prim_esc_test.3821260938 |
| /workspace/coverage/default/19.prim_esc_test.620560420 |
| /workspace/coverage/default/2.prim_esc_test.4056776010 |
| /workspace/coverage/default/4.prim_esc_test.208303774 |
| /workspace/coverage/default/5.prim_esc_test.1713524421 |
| /workspace/coverage/default/6.prim_esc_test.1145530307 |
| /workspace/coverage/default/7.prim_esc_test.931923048 |
| /workspace/coverage/default/9.prim_esc_test.2383808810 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_esc_test.3821260938 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:38 PM PDT 24 | 4782760 ps | ||
| T2 | /workspace/coverage/default/3.prim_esc_test.746014697 | Jun 04 12:45:29 PM PDT 24 | Jun 04 12:45:31 PM PDT 24 | 4560405 ps | ||
| T3 | /workspace/coverage/default/6.prim_esc_test.1145530307 | Jun 04 12:44:26 PM PDT 24 | Jun 04 12:44:28 PM PDT 24 | 5103311 ps | ||
| T4 | /workspace/coverage/default/11.prim_esc_test.3360312023 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:38 PM PDT 24 | 4667259 ps | ||
| T5 | /workspace/coverage/default/15.prim_esc_test.4175985508 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:36 PM PDT 24 | 4316867 ps | ||
| T8 | /workspace/coverage/default/8.prim_esc_test.2493584494 | Jun 04 12:44:34 PM PDT 24 | Jun 04 12:44:35 PM PDT 24 | 5246880 ps | ||
| T11 | /workspace/coverage/default/4.prim_esc_test.208303774 | Jun 04 12:45:29 PM PDT 24 | Jun 04 12:45:31 PM PDT 24 | 5271780 ps | ||
| T6 | /workspace/coverage/default/16.prim_esc_test.2912260913 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:37 PM PDT 24 | 5162109 ps | ||
| T9 | /workspace/coverage/default/1.prim_esc_test.1537601921 | Jun 04 12:44:23 PM PDT 24 | Jun 04 12:44:25 PM PDT 24 | 5441801 ps | ||
| T7 | /workspace/coverage/default/5.prim_esc_test.1713524421 | Jun 04 12:44:23 PM PDT 24 | Jun 04 12:44:24 PM PDT 24 | 5462000 ps | ||
| T15 | /workspace/coverage/default/13.prim_esc_test.75345682 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:38 PM PDT 24 | 4576314 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.628995295 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:38 PM PDT 24 | 4383163 ps | ||
| T13 | /workspace/coverage/default/19.prim_esc_test.620560420 | Jun 04 12:44:39 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 4829224 ps | ||
| T10 | /workspace/coverage/default/12.prim_esc_test.3603889948 | Jun 04 12:44:38 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 4772312 ps | ||
| T16 | /workspace/coverage/default/9.prim_esc_test.2383808810 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:42 PM PDT 24 | 4842965 ps | ||
| T17 | /workspace/coverage/default/7.prim_esc_test.931923048 | Jun 04 12:44:34 PM PDT 24 | Jun 04 12:44:36 PM PDT 24 | 4579963 ps | ||
| T18 | /workspace/coverage/default/10.prim_esc_test.3395923187 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:36 PM PDT 24 | 4753994 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.3786795000 | Jun 04 12:44:23 PM PDT 24 | Jun 04 12:44:25 PM PDT 24 | 4655829 ps | ||
| T19 | /workspace/coverage/default/2.prim_esc_test.4056776010 | Jun 04 12:44:24 PM PDT 24 | Jun 04 12:44:26 PM PDT 24 | 5191972 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.3289331483 | Jun 04 12:44:39 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 4515215 ps |
| Test location | /workspace/coverage/default/8.prim_esc_test.2493584494 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5246880 ps |
| CPU time | 0.39 seconds |
| Started | Jun 04 12:44:34 PM PDT 24 |
| Finished | Jun 04 12:44:35 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-0a4562af-7379-45ae-b169-c24dca753bc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493584494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2493584494 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.628995295 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4383163 ps |
| CPU time | 0.41 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:38 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-bf9e6df3-3d73-4999-9cd0-6d5f53ca9bc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628995295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.628995295 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.746014697 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4560405 ps |
| CPU time | 0.43 seconds |
| Started | Jun 04 12:45:29 PM PDT 24 |
| Finished | Jun 04 12:45:31 PM PDT 24 |
| Peak memory | 143856 kb |
| Host | smart-622485bf-1173-43b7-898c-1e9cca14b6a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746014697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.746014697 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3786795000 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4655829 ps |
| CPU time | 0.43 seconds |
| Started | Jun 04 12:44:23 PM PDT 24 |
| Finished | Jun 04 12:44:25 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-69453aa3-afd2-495e-a8d9-c8f53e38ecbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3786795000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3786795000 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3603889948 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4772312 ps |
| CPU time | 0.37 seconds |
| Started | Jun 04 12:44:38 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 145956 kb |
| Host | smart-b36fba7f-6014-40c5-8c8a-f2ba790b08a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603889948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3603889948 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1537601921 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5441801 ps |
| CPU time | 0.4 seconds |
| Started | Jun 04 12:44:23 PM PDT 24 |
| Finished | Jun 04 12:44:25 PM PDT 24 |
| Peak memory | 145920 kb |
| Host | smart-8d8a765c-e495-4f04-bda7-6d48c80999d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537601921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1537601921 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3395923187 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4753994 ps |
| CPU time | 0.39 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:36 PM PDT 24 |
| Peak memory | 146036 kb |
| Host | smart-fe1989be-2386-47bb-879c-1f83ac1243b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395923187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3395923187 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3360312023 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4667259 ps |
| CPU time | 0.42 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:38 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-88376993-cba8-4634-aea9-9a382ff07df1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360312023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3360312023 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.75345682 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4576314 ps |
| CPU time | 0.38 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:38 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-c4051585-92ad-48f4-b33f-d1c402951231 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75345682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.75345682 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4175985508 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4316867 ps |
| CPU time | 0.41 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:36 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-61da3a35-d1eb-45a9-b872-5005e9547b59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175985508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4175985508 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2912260913 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5162109 ps |
| CPU time | 0.43 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:37 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-cb01042c-39f7-4ead-bc4e-f812c8a1b9dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912260913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2912260913 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3289331483 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4515215 ps |
| CPU time | 0.38 seconds |
| Started | Jun 04 12:44:39 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-5621b4c0-e14a-4995-b4e7-3b9b38fac4ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3289331483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3289331483 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3821260938 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4782760 ps |
| CPU time | 0.39 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:38 PM PDT 24 |
| Peak memory | 146000 kb |
| Host | smart-365ce1e8-b692-4b30-aaeb-e4a12dac4e97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821260938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3821260938 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.620560420 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4829224 ps |
| CPU time | 0.38 seconds |
| Started | Jun 04 12:44:39 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 145976 kb |
| Host | smart-f90724b3-130f-48a0-b8aa-4d2a53384d91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620560420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.620560420 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.4056776010 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5191972 ps |
| CPU time | 0.38 seconds |
| Started | Jun 04 12:44:24 PM PDT 24 |
| Finished | Jun 04 12:44:26 PM PDT 24 |
| Peak memory | 145964 kb |
| Host | smart-0dd360cd-1e49-423c-8a0c-69ea2844c925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056776010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4056776010 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.208303774 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5271780 ps |
| CPU time | 0.39 seconds |
| Started | Jun 04 12:45:29 PM PDT 24 |
| Finished | Jun 04 12:45:31 PM PDT 24 |
| Peak memory | 143768 kb |
| Host | smart-0392bdc9-c450-4bf9-bc8f-01ef2076a0a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208303774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.208303774 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1713524421 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5462000 ps |
| CPU time | 0.38 seconds |
| Started | Jun 04 12:44:23 PM PDT 24 |
| Finished | Jun 04 12:44:24 PM PDT 24 |
| Peak memory | 146064 kb |
| Host | smart-bb067de6-75dd-4250-8f46-7e804f2a2387 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713524421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1713524421 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1145530307 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5103311 ps |
| CPU time | 0.4 seconds |
| Started | Jun 04 12:44:26 PM PDT 24 |
| Finished | Jun 04 12:44:28 PM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-518212e5-8de4-439a-b270-bf0d90a440cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145530307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1145530307 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.931923048 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4579963 ps |
| CPU time | 0.39 seconds |
| Started | Jun 04 12:44:34 PM PDT 24 |
| Finished | Jun 04 12:44:36 PM PDT 24 |
| Peak memory | 146040 kb |
| Host | smart-0ae460b8-8176-4db5-8feb-c73c4dfa3b35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931923048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.931923048 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2383808810 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4842965 ps |
| CPU time | 0.37 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:42 PM PDT 24 |
| Peak memory | 145964 kb |
| Host | smart-382f90e7-1ba5-4b49-b2b5-6b6b5d634f7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383808810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2383808810 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |