| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/13.prim_esc_test.3994910401 |
| 87.67 | 2.14 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.1978796654 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/6.prim_esc_test.3579846545 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/5.prim_esc_test.3668941063 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.2220816230 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2897826434 |
| /workspace/coverage/default/1.prim_esc_test.497179528 |
| /workspace/coverage/default/10.prim_esc_test.1245713265 |
| /workspace/coverage/default/11.prim_esc_test.2028790391 |
| /workspace/coverage/default/12.prim_esc_test.4205730004 |
| /workspace/coverage/default/14.prim_esc_test.60746435 |
| /workspace/coverage/default/15.prim_esc_test.2709958669 |
| /workspace/coverage/default/17.prim_esc_test.1564473328 |
| /workspace/coverage/default/18.prim_esc_test.1419095250 |
| /workspace/coverage/default/19.prim_esc_test.1457340327 |
| /workspace/coverage/default/2.prim_esc_test.1798255383 |
| /workspace/coverage/default/3.prim_esc_test.3645796299 |
| /workspace/coverage/default/4.prim_esc_test.3163514731 |
| /workspace/coverage/default/8.prim_esc_test.1664008691 |
| /workspace/coverage/default/9.prim_esc_test.3164377137 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_esc_test.60746435 | Jun 05 05:00:48 PM PDT 24 | Jun 05 05:00:49 PM PDT 24 | 5039258 ps | ||
| T2 | /workspace/coverage/default/4.prim_esc_test.3163514731 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:48 PM PDT 24 | 4730431 ps | ||
| T3 | /workspace/coverage/default/5.prim_esc_test.3668941063 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:48 PM PDT 24 | 4736170 ps | ||
| T5 | /workspace/coverage/default/10.prim_esc_test.1245713265 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:48 PM PDT 24 | 5026334 ps | ||
| T7 | /workspace/coverage/default/13.prim_esc_test.3994910401 | Jun 05 05:00:49 PM PDT 24 | Jun 05 05:00:50 PM PDT 24 | 4518974 ps | ||
| T8 | /workspace/coverage/default/2.prim_esc_test.1798255383 | Jun 05 05:00:46 PM PDT 24 | Jun 05 05:00:47 PM PDT 24 | 5014055 ps | ||
| T4 | /workspace/coverage/default/0.prim_esc_test.2897826434 | Jun 05 05:00:38 PM PDT 24 | Jun 05 05:00:39 PM PDT 24 | 4340242 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.1564473328 | Jun 05 05:00:49 PM PDT 24 | Jun 05 05:00:50 PM PDT 24 | 4893497 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.2028790391 | Jun 05 05:00:46 PM PDT 24 | Jun 05 05:00:47 PM PDT 24 | 4488635 ps | ||
| T13 | /workspace/coverage/default/12.prim_esc_test.4205730004 | Jun 05 05:00:48 PM PDT 24 | Jun 05 05:00:49 PM PDT 24 | 4737461 ps | ||
| T10 | /workspace/coverage/default/7.prim_esc_test.2220816230 | Jun 05 05:00:48 PM PDT 24 | Jun 05 05:00:49 PM PDT 24 | 4791551 ps | ||
| T14 | /workspace/coverage/default/3.prim_esc_test.3645796299 | Jun 05 05:00:48 PM PDT 24 | Jun 05 05:00:49 PM PDT 24 | 5088122 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.2709958669 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:48 PM PDT 24 | 4745511 ps | ||
| T6 | /workspace/coverage/default/6.prim_esc_test.3579846545 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:48 PM PDT 24 | 4538337 ps | ||
| T16 | /workspace/coverage/default/18.prim_esc_test.1419095250 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:48 PM PDT 24 | 4550194 ps | ||
| T17 | /workspace/coverage/default/19.prim_esc_test.1457340327 | Jun 05 05:00:48 PM PDT 24 | Jun 05 05:00:49 PM PDT 24 | 4952466 ps | ||
| T11 | /workspace/coverage/default/8.prim_esc_test.1664008691 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:00:47 PM PDT 24 | 4774298 ps | ||
| T18 | /workspace/coverage/default/9.prim_esc_test.3164377137 | Jun 05 05:00:55 PM PDT 24 | Jun 05 05:00:56 PM PDT 24 | 4913284 ps | ||
| T19 | /workspace/coverage/default/16.prim_esc_test.1978796654 | Jun 05 05:00:48 PM PDT 24 | Jun 05 05:00:49 PM PDT 24 | 4722931 ps | ||
| T20 | /workspace/coverage/default/1.prim_esc_test.497179528 | Jun 05 05:00:40 PM PDT 24 | Jun 05 05:00:41 PM PDT 24 | 4652879 ps |
| Test location | /workspace/coverage/default/13.prim_esc_test.3994910401 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4518974 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:49 PM PDT 24 |
| Finished | Jun 05 05:00:50 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-572ad735-6a81-4e5c-82b1-5060033a38db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994910401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3994910401 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1978796654 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4722931 ps |
| CPU time | 0.37 seconds |
| Started | Jun 05 05:00:48 PM PDT 24 |
| Finished | Jun 05 05:00:49 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-bdfc8a7d-b099-4e6a-833c-5d23c71f3794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978796654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1978796654 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3579846545 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4538337 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:48 PM PDT 24 |
| Peak memory | 146116 kb |
| Host | smart-4cdcf89f-68db-433e-8073-8ba09356333f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579846545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3579846545 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3668941063 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4736170 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:48 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-a119b238-6df9-4c1b-bb4e-0d11b6b4807c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668941063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3668941063 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2220816230 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4791551 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:48 PM PDT 24 |
| Finished | Jun 05 05:00:49 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-b1cfe84c-a36b-47e2-9e11-0d89447946d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220816230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2220816230 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2897826434 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4340242 ps |
| CPU time | 0.39 seconds |
| Started | Jun 05 05:00:38 PM PDT 24 |
| Finished | Jun 05 05:00:39 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-ea63b66a-fb8f-4fb7-8a52-c02ced248488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897826434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2897826434 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.497179528 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4652879 ps |
| CPU time | 0.37 seconds |
| Started | Jun 05 05:00:40 PM PDT 24 |
| Finished | Jun 05 05:00:41 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-01689c63-5369-46d5-9bf0-bcc8459b9588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497179528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.497179528 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1245713265 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5026334 ps |
| CPU time | 0.39 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:48 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-b45e8219-9aa4-480c-a9ef-18d32edd554e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245713265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1245713265 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2028790391 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4488635 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:46 PM PDT 24 |
| Finished | Jun 05 05:00:47 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-81bf39ce-507b-472f-84ff-ad76892761ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028790391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2028790391 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.4205730004 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4737461 ps |
| CPU time | 0.39 seconds |
| Started | Jun 05 05:00:48 PM PDT 24 |
| Finished | Jun 05 05:00:49 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-e235a237-16d2-45e5-b7f6-3432e1755d26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205730004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4205730004 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.60746435 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5039258 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:48 PM PDT 24 |
| Finished | Jun 05 05:00:49 PM PDT 24 |
| Peak memory | 146204 kb |
| Host | smart-a609aa73-9fc1-4f58-9c5a-4f2f4f0b013d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60746435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.60746435 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2709958669 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4745511 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:48 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-265a1bf6-9316-4694-bdda-9d0f970cd15c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709958669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2709958669 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1564473328 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4893497 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:49 PM PDT 24 |
| Finished | Jun 05 05:00:50 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-38121abb-18a3-4822-b461-402065f8f6f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564473328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1564473328 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1419095250 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4550194 ps |
| CPU time | 0.36 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:48 PM PDT 24 |
| Peak memory | 146180 kb |
| Host | smart-e8029496-e65a-436b-a7b9-15ad376abc3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419095250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1419095250 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1457340327 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4952466 ps |
| CPU time | 0.37 seconds |
| Started | Jun 05 05:00:48 PM PDT 24 |
| Finished | Jun 05 05:00:49 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-3137021c-a8b3-46dc-856d-8776f226a30b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457340327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1457340327 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1798255383 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5014055 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:46 PM PDT 24 |
| Finished | Jun 05 05:00:47 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-bdfa4909-f2e5-4cb5-aa1f-a2885df84a8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798255383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1798255383 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3645796299 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5088122 ps |
| CPU time | 0.37 seconds |
| Started | Jun 05 05:00:48 PM PDT 24 |
| Finished | Jun 05 05:00:49 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-bfe947ec-9919-4391-9507-7e79fff857e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645796299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3645796299 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3163514731 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4730431 ps |
| CPU time | 0.37 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:48 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-308f2ede-0fc6-49b1-9337-65b10be71611 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163514731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3163514731 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1664008691 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4774298 ps |
| CPU time | 0.38 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:00:47 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-cb249ba4-2d7e-4778-ba01-9e88a2837cce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664008691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1664008691 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3164377137 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4913284 ps |
| CPU time | 0.37 seconds |
| Started | Jun 05 05:00:55 PM PDT 24 |
| Finished | Jun 05 05:00:56 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-8174c70f-856b-4783-8508-9f6bc13cd262 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164377137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3164377137 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |