| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 88.71 | 92.38 | 85.37 | 100.00 | 89.29 | 83.72 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.83 | 84.83 | 90.48 | 90.48 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/0.prim_esc_test.3570296290 |
| 86.97 | 2.14 | 91.43 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 81.40 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3397967425 |
| 88.71 | 1.74 | 92.38 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.936522260 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.2594054934 |
| /workspace/coverage/default/10.prim_esc_test.3391363793 |
| /workspace/coverage/default/11.prim_esc_test.3520499808 |
| /workspace/coverage/default/12.prim_esc_test.3221700421 |
| /workspace/coverage/default/14.prim_esc_test.1704047670 |
| /workspace/coverage/default/15.prim_esc_test.859713607 |
| /workspace/coverage/default/16.prim_esc_test.2658215382 |
| /workspace/coverage/default/17.prim_esc_test.1098480380 |
| /workspace/coverage/default/18.prim_esc_test.3735500917 |
| /workspace/coverage/default/19.prim_esc_test.2663207711 |
| /workspace/coverage/default/3.prim_esc_test.3895002403 |
| /workspace/coverage/default/4.prim_esc_test.3068219251 |
| /workspace/coverage/default/5.prim_esc_test.912798980 |
| /workspace/coverage/default/6.prim_esc_test.4201787021 |
| /workspace/coverage/default/7.prim_esc_test.1725894014 |
| /workspace/coverage/default/8.prim_esc_test.3536133539 |
| /workspace/coverage/default/9.prim_esc_test.3934806905 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_esc_test.3397967425 | Jun 06 02:13:22 PM PDT 24 | Jun 06 02:13:24 PM PDT 24 | 4371062 ps | ||
| T2 | /workspace/coverage/default/15.prim_esc_test.859713607 | Jun 06 02:13:20 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 5094787 ps | ||
| T3 | /workspace/coverage/default/12.prim_esc_test.3221700421 | Jun 06 02:13:26 PM PDT 24 | Jun 06 02:13:27 PM PDT 24 | 5138471 ps | ||
| T6 | /workspace/coverage/default/0.prim_esc_test.3570296290 | Jun 06 02:13:24 PM PDT 24 | Jun 06 02:13:26 PM PDT 24 | 5220150 ps | ||
| T7 | /workspace/coverage/default/8.prim_esc_test.3536133539 | Jun 06 02:13:39 PM PDT 24 | Jun 06 02:13:40 PM PDT 24 | 4971320 ps | ||
| T8 | /workspace/coverage/default/1.prim_esc_test.2594054934 | Jun 06 02:13:25 PM PDT 24 | Jun 06 02:13:26 PM PDT 24 | 4679016 ps | ||
| T9 | /workspace/coverage/default/19.prim_esc_test.2663207711 | Jun 06 02:13:24 PM PDT 24 | Jun 06 02:13:25 PM PDT 24 | 5082030 ps | ||
| T4 | /workspace/coverage/default/17.prim_esc_test.1098480380 | Jun 06 02:13:19 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 4591882 ps | ||
| T5 | /workspace/coverage/default/6.prim_esc_test.4201787021 | Jun 06 02:13:26 PM PDT 24 | Jun 06 02:13:27 PM PDT 24 | 4770769 ps | ||
| T10 | /workspace/coverage/default/18.prim_esc_test.3735500917 | Jun 06 02:13:21 PM PDT 24 | Jun 06 02:13:23 PM PDT 24 | 4531071 ps | ||
| T12 | /workspace/coverage/default/10.prim_esc_test.3391363793 | Jun 06 02:13:22 PM PDT 24 | Jun 06 02:13:24 PM PDT 24 | 4938429 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.2658215382 | Jun 06 02:13:24 PM PDT 24 | Jun 06 02:13:26 PM PDT 24 | 4324648 ps | ||
| T17 | /workspace/coverage/default/14.prim_esc_test.1704047670 | Jun 06 02:13:24 PM PDT 24 | Jun 06 02:13:26 PM PDT 24 | 4938805 ps | ||
| T18 | /workspace/coverage/default/5.prim_esc_test.912798980 | Jun 06 02:13:24 PM PDT 24 | Jun 06 02:13:25 PM PDT 24 | 5142160 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.3068219251 | Jun 06 02:13:31 PM PDT 24 | Jun 06 02:13:32 PM PDT 24 | 5275770 ps | ||
| T11 | /workspace/coverage/default/3.prim_esc_test.3895002403 | Jun 06 02:13:31 PM PDT 24 | Jun 06 02:13:32 PM PDT 24 | 4609147 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.3520499808 | Jun 06 02:13:25 PM PDT 24 | Jun 06 02:13:27 PM PDT 24 | 4425520 ps | ||
| T13 | /workspace/coverage/default/9.prim_esc_test.3934806905 | Jun 06 02:13:28 PM PDT 24 | Jun 06 02:13:29 PM PDT 24 | 4952400 ps | ||
| T20 | /workspace/coverage/default/7.prim_esc_test.1725894014 | Jun 06 02:13:36 PM PDT 24 | Jun 06 02:13:37 PM PDT 24 | 5024156 ps | ||
| T14 | /workspace/coverage/default/2.prim_esc_test.936522260 | Jun 06 02:13:20 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 5106856 ps |
| Test location | /workspace/coverage/default/0.prim_esc_test.3570296290 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5220150 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:24 PM PDT 24 |
| Finished | Jun 06 02:13:26 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-dca729d2-6181-4b43-8ef6-f985e52d528e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570296290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3570296290 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3397967425 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4371062 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:22 PM PDT 24 |
| Finished | Jun 06 02:13:24 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-0e6bcf83-6f34-4211-bf60-29f244864540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397967425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3397967425 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.936522260 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5106856 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:20 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-c18b64f3-1f82-4508-a52a-c107547df4ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936522260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.936522260 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2594054934 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4679016 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:25 PM PDT 24 |
| Finished | Jun 06 02:13:26 PM PDT 24 |
| Peak memory | 146120 kb |
| Host | smart-dfe4fcdc-c246-4528-9223-f8633cdca414 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594054934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2594054934 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3391363793 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4938429 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:22 PM PDT 24 |
| Finished | Jun 06 02:13:24 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-8b9e1890-9a20-4bde-ad52-1af2c28dd121 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391363793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3391363793 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3520499808 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4425520 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:25 PM PDT 24 |
| Finished | Jun 06 02:13:27 PM PDT 24 |
| Peak memory | 146212 kb |
| Host | smart-b0c1cb79-884a-4882-820c-8ce8b470d6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520499808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3520499808 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3221700421 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5138471 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:26 PM PDT 24 |
| Finished | Jun 06 02:13:27 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-02d85eae-995b-4eca-967b-946a9307cab6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221700421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3221700421 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1704047670 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4938805 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 02:13:24 PM PDT 24 |
| Finished | Jun 06 02:13:26 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-a91b210a-f87d-4460-92b8-bc5ccad142e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704047670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1704047670 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.859713607 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5094787 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 02:13:20 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 146172 kb |
| Host | smart-30195e1a-747b-48ac-b668-521d74a9fe84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859713607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.859713607 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2658215382 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4324648 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:24 PM PDT 24 |
| Finished | Jun 06 02:13:26 PM PDT 24 |
| Peak memory | 146184 kb |
| Host | smart-966c21af-4260-4898-b3ef-b2008b5162ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658215382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2658215382 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1098480380 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4591882 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:19 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-5ddbcfb1-ba17-420a-8fbb-24e8d74a384c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098480380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1098480380 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3735500917 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4531071 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:21 PM PDT 24 |
| Finished | Jun 06 02:13:23 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-3890d5ff-0986-43e0-a6a2-2ee256762f43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735500917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3735500917 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2663207711 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5082030 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:24 PM PDT 24 |
| Finished | Jun 06 02:13:25 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-98cffdab-58d8-4bce-95e7-9a275a9d9d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663207711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2663207711 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3895002403 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4609147 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:31 PM PDT 24 |
| Finished | Jun 06 02:13:32 PM PDT 24 |
| Peak memory | 146068 kb |
| Host | smart-9d0856e5-ef5e-4e84-9a0e-2996d88eb3a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895002403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3895002403 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3068219251 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5275770 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:31 PM PDT 24 |
| Finished | Jun 06 02:13:32 PM PDT 24 |
| Peak memory | 146236 kb |
| Host | smart-5ba33149-4932-4d73-a406-636ef772c547 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068219251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3068219251 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.912798980 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5142160 ps |
| CPU time | 0.36 seconds |
| Started | Jun 06 02:13:24 PM PDT 24 |
| Finished | Jun 06 02:13:25 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-16a444e8-42c7-4070-90ac-2a9d8df91bf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912798980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.912798980 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4201787021 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4770769 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:26 PM PDT 24 |
| Finished | Jun 06 02:13:27 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-03d32029-6c52-4c90-81a8-3eb917cae277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201787021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4201787021 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1725894014 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5024156 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 02:13:36 PM PDT 24 |
| Finished | Jun 06 02:13:37 PM PDT 24 |
| Peak memory | 146120 kb |
| Host | smart-4779791a-1460-4314-b28f-947c12ede2a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725894014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1725894014 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3536133539 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4971320 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:39 PM PDT 24 |
| Finished | Jun 06 02:13:40 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-1c49bb51-3bc8-4058-aa47-cd6576b7d9d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536133539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3536133539 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3934806905 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4952400 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:28 PM PDT 24 |
| Finished | Jun 06 02:13:29 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-83fc4989-b374-4a93-a32a-5ca67efbcde7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934806905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3934806905 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |