Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.13 86.13 92.38 92.38 82.93 82.93 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/9.prim_esc_test.1331708808
88.86 2.74 93.33 0.95 85.37 2.44 100.00 0.00 89.29 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/4.prim_esc_test.3483170723
90.01 1.14 94.29 0.95 85.37 0.00 100.00 0.00 92.86 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.4122124393
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/14.prim_esc_test.1551747154

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.3598354200
/workspace/coverage/default/10.prim_esc_test.3166667787
/workspace/coverage/default/11.prim_esc_test.1246888573
/workspace/coverage/default/12.prim_esc_test.199607146
/workspace/coverage/default/13.prim_esc_test.1666758967
/workspace/coverage/default/15.prim_esc_test.1560597687
/workspace/coverage/default/16.prim_esc_test.1721233394
/workspace/coverage/default/17.prim_esc_test.3205203963
/workspace/coverage/default/18.prim_esc_test.2531300973
/workspace/coverage/default/19.prim_esc_test.3103785451
/workspace/coverage/default/2.prim_esc_test.2957801986
/workspace/coverage/default/3.prim_esc_test.3317487936
/workspace/coverage/default/5.prim_esc_test.1221030819
/workspace/coverage/default/6.prim_esc_test.3479959085
/workspace/coverage/default/7.prim_esc_test.1212170002
/workspace/coverage/default/8.prim_esc_test.249992857



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/19.prim_esc_test.3103785451 Jun 07 07:56:58 PM PDT 24 Jun 07 07:57:03 PM PDT 24 4642602 ps
T2 /workspace/coverage/default/18.prim_esc_test.2531300973 Jun 07 07:56:58 PM PDT 24 Jun 07 07:57:03 PM PDT 24 4424986 ps
T3 /workspace/coverage/default/12.prim_esc_test.199607146 Jun 07 07:56:58 PM PDT 24 Jun 07 07:57:03 PM PDT 24 5035477 ps
T6 /workspace/coverage/default/5.prim_esc_test.1221030819 Jun 07 07:56:53 PM PDT 24 Jun 07 07:56:59 PM PDT 24 4918691 ps
T4 /workspace/coverage/default/6.prim_esc_test.3479959085 Jun 07 07:56:50 PM PDT 24 Jun 07 07:56:56 PM PDT 24 4452176 ps
T5 /workspace/coverage/default/2.prim_esc_test.2957801986 Jun 07 07:56:50 PM PDT 24 Jun 07 07:56:56 PM PDT 24 4442902 ps
T8 /workspace/coverage/default/9.prim_esc_test.1331708808 Jun 07 07:56:53 PM PDT 24 Jun 07 07:56:59 PM PDT 24 4308544 ps
T7 /workspace/coverage/default/8.prim_esc_test.249992857 Jun 07 07:56:52 PM PDT 24 Jun 07 07:56:58 PM PDT 24 4887440 ps
T15 /workspace/coverage/default/17.prim_esc_test.3205203963 Jun 07 07:56:55 PM PDT 24 Jun 07 07:57:01 PM PDT 24 5276514 ps
T10 /workspace/coverage/default/4.prim_esc_test.3483170723 Jun 07 07:56:53 PM PDT 24 Jun 07 07:56:58 PM PDT 24 4965049 ps
T16 /workspace/coverage/default/14.prim_esc_test.1551747154 Jun 07 07:56:57 PM PDT 24 Jun 07 07:57:02 PM PDT 24 5082926 ps
T9 /workspace/coverage/default/3.prim_esc_test.3317487936 Jun 07 07:56:48 PM PDT 24 Jun 07 07:56:52 PM PDT 24 4438766 ps
T11 /workspace/coverage/default/10.prim_esc_test.3166667787 Jun 07 07:56:49 PM PDT 24 Jun 07 07:56:55 PM PDT 24 4382424 ps
T17 /workspace/coverage/default/13.prim_esc_test.1666758967 Jun 07 07:56:59 PM PDT 24 Jun 07 07:57:04 PM PDT 24 5283108 ps
T18 /workspace/coverage/default/16.prim_esc_test.1721233394 Jun 07 07:56:59 PM PDT 24 Jun 07 07:57:04 PM PDT 24 5313831 ps
T12 /workspace/coverage/default/11.prim_esc_test.1246888573 Jun 07 07:56:51 PM PDT 24 Jun 07 07:56:56 PM PDT 24 5110488 ps
T14 /workspace/coverage/default/0.prim_esc_test.4122124393 Jun 07 07:56:51 PM PDT 24 Jun 07 07:56:57 PM PDT 24 4259852 ps
T19 /workspace/coverage/default/15.prim_esc_test.1560597687 Jun 07 07:56:57 PM PDT 24 Jun 07 07:57:02 PM PDT 24 4986876 ps
T20 /workspace/coverage/default/7.prim_esc_test.1212170002 Jun 07 07:56:49 PM PDT 24 Jun 07 07:56:55 PM PDT 24 5256386 ps
T13 /workspace/coverage/default/1.prim_esc_test.3598354200 Jun 07 07:56:51 PM PDT 24 Jun 07 07:56:57 PM PDT 24 4909316 ps

Test location /workspace/coverage/default/9.prim_esc_test.1331708808
Short name T8
Test name
Test status
Simulation time 4308544 ps
CPU time 0.4 seconds
Started Jun 07 07:56:53 PM PDT 24
Finished Jun 07 07:56:59 PM PDT 24
Peak memory 147388 kb
Host smart-bcc772fc-9ba4-4e87-abd4-a4658d003aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331708808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1331708808
Directory /workspace/9.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3483170723
Short name T10
Test name
Test status
Simulation time 4965049 ps
CPU time 0.37 seconds
Started Jun 07 07:56:53 PM PDT 24
Finished Jun 07 07:56:58 PM PDT 24
Peak memory 146124 kb
Host smart-e1494c51-6f90-45fc-9410-9c3148f221fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483170723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3483170723
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.4122124393
Short name T14
Test name
Test status
Simulation time 4259852 ps
CPU time 0.38 seconds
Started Jun 07 07:56:51 PM PDT 24
Finished Jun 07 07:56:57 PM PDT 24
Peak memory 145976 kb
Host smart-7d769b56-c714-4fb3-b959-464d0873a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122124393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4122124393
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1551747154
Short name T16
Test name
Test status
Simulation time 5082926 ps
CPU time 0.38 seconds
Started Jun 07 07:56:57 PM PDT 24
Finished Jun 07 07:57:02 PM PDT 24
Peak memory 146236 kb
Host smart-6be246bd-00da-4c18-a457-889256c56e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551747154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1551747154
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3598354200
Short name T13
Test name
Test status
Simulation time 4909316 ps
CPU time 0.38 seconds
Started Jun 07 07:56:51 PM PDT 24
Finished Jun 07 07:56:57 PM PDT 24
Peak memory 145944 kb
Host smart-93265db4-045c-43f7-ae6b-830780d846d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598354200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3598354200
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3166667787
Short name T11
Test name
Test status
Simulation time 4382424 ps
CPU time 0.39 seconds
Started Jun 07 07:56:49 PM PDT 24
Finished Jun 07 07:56:55 PM PDT 24
Peak memory 146204 kb
Host smart-01899042-1a46-49df-8ac3-4daadcf5a481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166667787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3166667787
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1246888573
Short name T12
Test name
Test status
Simulation time 5110488 ps
CPU time 0.41 seconds
Started Jun 07 07:56:51 PM PDT 24
Finished Jun 07 07:56:56 PM PDT 24
Peak memory 146244 kb
Host smart-1130a5db-058c-464a-a4fc-a49a014d830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246888573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1246888573
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.199607146
Short name T3
Test name
Test status
Simulation time 5035477 ps
CPU time 0.39 seconds
Started Jun 07 07:56:58 PM PDT 24
Finished Jun 07 07:57:03 PM PDT 24
Peak memory 146264 kb
Host smart-d8389864-e305-4c58-ab24-3168f09bb9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199607146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.199607146
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1666758967
Short name T17
Test name
Test status
Simulation time 5283108 ps
CPU time 0.37 seconds
Started Jun 07 07:56:59 PM PDT 24
Finished Jun 07 07:57:04 PM PDT 24
Peak memory 146128 kb
Host smart-271c9820-6bca-4cca-b965-9cfd7579b250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666758967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1666758967
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1560597687
Short name T19
Test name
Test status
Simulation time 4986876 ps
CPU time 0.39 seconds
Started Jun 07 07:56:57 PM PDT 24
Finished Jun 07 07:57:02 PM PDT 24
Peak memory 146236 kb
Host smart-6dc1f9d2-e99c-4b0b-91ec-f8b5d7979d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560597687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1560597687
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1721233394
Short name T18
Test name
Test status
Simulation time 5313831 ps
CPU time 0.37 seconds
Started Jun 07 07:56:59 PM PDT 24
Finished Jun 07 07:57:04 PM PDT 24
Peak memory 146228 kb
Host smart-72be1acb-fb87-4ff5-86ac-18a4671785c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721233394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1721233394
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3205203963
Short name T15
Test name
Test status
Simulation time 5276514 ps
CPU time 0.39 seconds
Started Jun 07 07:56:55 PM PDT 24
Finished Jun 07 07:57:01 PM PDT 24
Peak memory 146244 kb
Host smart-3d2f5d82-cfb1-4c86-996c-3093b88ef0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205203963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3205203963
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2531300973
Short name T2
Test name
Test status
Simulation time 4424986 ps
CPU time 0.41 seconds
Started Jun 07 07:56:58 PM PDT 24
Finished Jun 07 07:57:03 PM PDT 24
Peak memory 146232 kb
Host smart-1c81b879-2742-44c7-940f-10781dacad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531300973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2531300973
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3103785451
Short name T1
Test name
Test status
Simulation time 4642602 ps
CPU time 0.38 seconds
Started Jun 07 07:56:58 PM PDT 24
Finished Jun 07 07:57:03 PM PDT 24
Peak memory 146228 kb
Host smart-dc8fbb83-f680-4005-b84c-4b5f640e0e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103785451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3103785451
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2957801986
Short name T5
Test name
Test status
Simulation time 4442902 ps
CPU time 0.42 seconds
Started Jun 07 07:56:50 PM PDT 24
Finished Jun 07 07:56:56 PM PDT 24
Peak memory 146288 kb
Host smart-9c9e9767-0bcb-49ed-8912-c4b2f975249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957801986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2957801986
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3317487936
Short name T9
Test name
Test status
Simulation time 4438766 ps
CPU time 0.38 seconds
Started Jun 07 07:56:48 PM PDT 24
Finished Jun 07 07:56:52 PM PDT 24
Peak memory 146136 kb
Host smart-877850ba-a22d-4dd2-8146-f36196cb3afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317487936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3317487936
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1221030819
Short name T6
Test name
Test status
Simulation time 4918691 ps
CPU time 0.41 seconds
Started Jun 07 07:56:53 PM PDT 24
Finished Jun 07 07:56:59 PM PDT 24
Peak memory 147336 kb
Host smart-f62803b5-08a6-4c24-81f0-d39b686c1c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221030819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1221030819
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.3479959085
Short name T4
Test name
Test status
Simulation time 4452176 ps
CPU time 0.39 seconds
Started Jun 07 07:56:50 PM PDT 24
Finished Jun 07 07:56:56 PM PDT 24
Peak memory 146260 kb
Host smart-410b1ccd-659b-41f7-883c-22e8fe130803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479959085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3479959085
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.1212170002
Short name T20
Test name
Test status
Simulation time 5256386 ps
CPU time 0.38 seconds
Started Jun 07 07:56:49 PM PDT 24
Finished Jun 07 07:56:55 PM PDT 24
Peak memory 146104 kb
Host smart-6e56497a-8175-4dd4-999b-6c774779707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212170002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1212170002
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.249992857
Short name T7
Test name
Test status
Simulation time 4887440 ps
CPU time 0.37 seconds
Started Jun 07 07:56:52 PM PDT 24
Finished Jun 07 07:56:58 PM PDT 24
Peak memory 146144 kb
Host smart-5a0bc590-76bd-48ff-827f-7edfe58a3004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249992857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.249992857
Directory /workspace/8.prim_esc_test/latest
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