| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.01 | 94.29 | 85.37 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.64 | 84.64 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 71.43 | 71.43 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.2627534765 |
| 87.67 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 82.14 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2657132474 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.121790670 |
| 90.01 | 0.60 | 94.29 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2684211586 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.2975991202 |
| /workspace/coverage/default/11.prim_esc_test.2588898225 |
| /workspace/coverage/default/13.prim_esc_test.2656467687 |
| /workspace/coverage/default/14.prim_esc_test.3350160681 |
| /workspace/coverage/default/15.prim_esc_test.430408266 |
| /workspace/coverage/default/17.prim_esc_test.2487819268 |
| /workspace/coverage/default/18.prim_esc_test.2624936128 |
| /workspace/coverage/default/19.prim_esc_test.1787132575 |
| /workspace/coverage/default/2.prim_esc_test.3794739489 |
| /workspace/coverage/default/3.prim_esc_test.2365035762 |
| /workspace/coverage/default/4.prim_esc_test.458780802 |
| /workspace/coverage/default/5.prim_esc_test.35510637 |
| /workspace/coverage/default/6.prim_esc_test.3620718676 |
| /workspace/coverage/default/7.prim_esc_test.3408142774 |
| /workspace/coverage/default/8.prim_esc_test.3662721334 |
| /workspace/coverage/default/9.prim_esc_test.3602790449 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_esc_test.35510637 | Jun 09 12:27:43 PM PDT 24 | Jun 09 12:27:44 PM PDT 24 | 4915223 ps | ||
| T2 | /workspace/coverage/default/11.prim_esc_test.2588898225 | Jun 09 12:27:48 PM PDT 24 | Jun 09 12:27:49 PM PDT 24 | 4870632 ps | ||
| T3 | /workspace/coverage/default/16.prim_esc_test.121790670 | Jun 09 12:27:40 PM PDT 24 | Jun 09 12:27:41 PM PDT 24 | 5187119 ps | ||
| T4 | /workspace/coverage/default/9.prim_esc_test.3602790449 | Jun 09 12:28:08 PM PDT 24 | Jun 09 12:28:09 PM PDT 24 | 4984010 ps | ||
| T10 | /workspace/coverage/default/12.prim_esc_test.2627534765 | Jun 09 12:27:56 PM PDT 24 | Jun 09 12:27:58 PM PDT 24 | 5076825 ps | ||
| T11 | /workspace/coverage/default/4.prim_esc_test.458780802 | Jun 09 12:27:47 PM PDT 24 | Jun 09 12:27:48 PM PDT 24 | 4723113 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.2975991202 | Jun 09 12:27:53 PM PDT 24 | Jun 09 12:27:54 PM PDT 24 | 4710860 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.430408266 | Jun 09 12:27:53 PM PDT 24 | Jun 09 12:27:54 PM PDT 24 | 5028226 ps | ||
| T15 | /workspace/coverage/default/0.prim_esc_test.2684211586 | Jun 09 12:27:41 PM PDT 24 | Jun 09 12:27:42 PM PDT 24 | 4847673 ps | ||
| T5 | /workspace/coverage/default/19.prim_esc_test.1787132575 | Jun 09 12:27:48 PM PDT 24 | Jun 09 12:27:49 PM PDT 24 | 5058464 ps | ||
| T6 | /workspace/coverage/default/10.prim_esc_test.2657132474 | Jun 09 12:27:50 PM PDT 24 | Jun 09 12:27:51 PM PDT 24 | 5306459 ps | ||
| T13 | /workspace/coverage/default/2.prim_esc_test.3794739489 | Jun 09 12:27:46 PM PDT 24 | Jun 09 12:27:47 PM PDT 24 | 4654186 ps | ||
| T16 | /workspace/coverage/default/3.prim_esc_test.2365035762 | Jun 09 12:27:39 PM PDT 24 | Jun 09 12:27:40 PM PDT 24 | 4537925 ps | ||
| T8 | /workspace/coverage/default/13.prim_esc_test.2656467687 | Jun 09 12:28:17 PM PDT 24 | Jun 09 12:28:18 PM PDT 24 | 4603593 ps | ||
| T7 | /workspace/coverage/default/18.prim_esc_test.2624936128 | Jun 09 12:27:55 PM PDT 24 | Jun 09 12:27:56 PM PDT 24 | 4754870 ps | ||
| T9 | /workspace/coverage/default/17.prim_esc_test.2487819268 | Jun 09 12:27:53 PM PDT 24 | Jun 09 12:27:54 PM PDT 24 | 5286470 ps | ||
| T17 | /workspace/coverage/default/6.prim_esc_test.3620718676 | Jun 09 12:27:47 PM PDT 24 | Jun 09 12:27:47 PM PDT 24 | 5041439 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.3408142774 | Jun 09 12:27:47 PM PDT 24 | Jun 09 12:27:48 PM PDT 24 | 4485864 ps | ||
| T19 | /workspace/coverage/default/14.prim_esc_test.3350160681 | Jun 09 12:27:41 PM PDT 24 | Jun 09 12:27:42 PM PDT 24 | 5029479 ps | ||
| T20 | /workspace/coverage/default/8.prim_esc_test.3662721334 | Jun 09 12:27:51 PM PDT 24 | Jun 09 12:27:52 PM PDT 24 | 4982825 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.2627534765 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5076825 ps |
| CPU time | 0.4 seconds |
| Started | Jun 09 12:27:56 PM PDT 24 |
| Finished | Jun 09 12:27:58 PM PDT 24 |
| Peak memory | 146316 kb |
| Host | smart-5b2eda6b-9112-407d-8faf-23b366f1896e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627534765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2627534765 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2657132474 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5306459 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:50 PM PDT 24 |
| Finished | Jun 09 12:27:51 PM PDT 24 |
| Peak memory | 146048 kb |
| Host | smart-de1c121d-b492-418c-8390-b00ac70ac65e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657132474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2657132474 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.121790670 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5187119 ps |
| CPU time | 0.4 seconds |
| Started | Jun 09 12:27:40 PM PDT 24 |
| Finished | Jun 09 12:27:41 PM PDT 24 |
| Peak memory | 146016 kb |
| Host | smart-440f5e47-7872-444f-9bf9-a062776a7635 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121790670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.121790670 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2684211586 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4847673 ps |
| CPU time | 0.39 seconds |
| Started | Jun 09 12:27:41 PM PDT 24 |
| Finished | Jun 09 12:27:42 PM PDT 24 |
| Peak memory | 145940 kb |
| Host | smart-2ccb9720-90b2-4841-9607-5779036a3359 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684211586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2684211586 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2975991202 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4710860 ps |
| CPU time | 0.37 seconds |
| Started | Jun 09 12:27:53 PM PDT 24 |
| Finished | Jun 09 12:27:54 PM PDT 24 |
| Peak memory | 145944 kb |
| Host | smart-36c90647-d213-47f0-855f-3d4c2d63aa5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975991202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2975991202 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2588898225 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4870632 ps |
| CPU time | 0.39 seconds |
| Started | Jun 09 12:27:48 PM PDT 24 |
| Finished | Jun 09 12:27:49 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-8862bb7b-0f96-4512-8037-732c7e697339 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588898225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2588898225 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2656467687 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4603593 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:28:17 PM PDT 24 |
| Finished | Jun 09 12:28:18 PM PDT 24 |
| Peak memory | 146076 kb |
| Host | smart-3fb74895-f19f-4a33-895e-4db225bb9dda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656467687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2656467687 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3350160681 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5029479 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:41 PM PDT 24 |
| Finished | Jun 09 12:27:42 PM PDT 24 |
| Peak memory | 145988 kb |
| Host | smart-abf67bfb-69b2-40aa-a304-ae10d8092356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350160681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3350160681 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.430408266 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5028226 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:53 PM PDT 24 |
| Finished | Jun 09 12:27:54 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-82c4d8d5-13d8-41bd-83ca-e9c594a4c0eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430408266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.430408266 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2487819268 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5286470 ps |
| CPU time | 0.37 seconds |
| Started | Jun 09 12:27:53 PM PDT 24 |
| Finished | Jun 09 12:27:54 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-178c5a48-49f0-4984-9707-ad5187b6e049 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487819268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2487819268 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2624936128 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4754870 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:55 PM PDT 24 |
| Finished | Jun 09 12:27:56 PM PDT 24 |
| Peak memory | 146068 kb |
| Host | smart-5beb7953-75fd-43ac-9776-1f3063a9fa5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624936128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2624936128 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1787132575 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5058464 ps |
| CPU time | 0.37 seconds |
| Started | Jun 09 12:27:48 PM PDT 24 |
| Finished | Jun 09 12:27:49 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-7f3431da-82b9-485f-9de1-d391fcce6b32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787132575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1787132575 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3794739489 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4654186 ps |
| CPU time | 0.41 seconds |
| Started | Jun 09 12:27:46 PM PDT 24 |
| Finished | Jun 09 12:27:47 PM PDT 24 |
| Peak memory | 145944 kb |
| Host | smart-3a602071-9d68-42da-b51e-ee7e70fd3dd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794739489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3794739489 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2365035762 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4537925 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:39 PM PDT 24 |
| Finished | Jun 09 12:27:40 PM PDT 24 |
| Peak memory | 145944 kb |
| Host | smart-adc47969-183d-4597-80c1-cac955e6da9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365035762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2365035762 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.458780802 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4723113 ps |
| CPU time | 0.4 seconds |
| Started | Jun 09 12:27:47 PM PDT 24 |
| Finished | Jun 09 12:27:48 PM PDT 24 |
| Peak memory | 146008 kb |
| Host | smart-89c3c7be-71c1-40da-b57a-d898168b3715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458780802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.458780802 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.35510637 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4915223 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:43 PM PDT 24 |
| Finished | Jun 09 12:27:44 PM PDT 24 |
| Peak memory | 146036 kb |
| Host | smart-55d2ec9b-e5f8-4f33-a95e-597a4c4caf96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35510637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.35510637 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3620718676 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5041439 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:47 PM PDT 24 |
| Finished | Jun 09 12:27:47 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-9d179dd4-228b-42c9-80ba-af02557a4707 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620718676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3620718676 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3408142774 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4485864 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:47 PM PDT 24 |
| Finished | Jun 09 12:27:48 PM PDT 24 |
| Peak memory | 145956 kb |
| Host | smart-2710eaa3-3fdb-4db1-bccd-89226f7499ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408142774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3408142774 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3662721334 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4982825 ps |
| CPU time | 0.38 seconds |
| Started | Jun 09 12:27:51 PM PDT 24 |
| Finished | Jun 09 12:27:52 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-f89dec4f-512e-4872-b6a5-c0538a840295 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662721334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3662721334 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3602790449 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4984010 ps |
| CPU time | 0.36 seconds |
| Started | Jun 09 12:28:08 PM PDT 24 |
| Finished | Jun 09 12:28:09 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-25dab341-9f9f-4f2c-8cc5-e094bd614c7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602790449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3602790449 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |