| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/3.prim_esc_test.513992788 |
| 87.67 | 2.14 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3515044254 |
| 88.82 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.152416681 |
| 89.96 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/5.prim_esc_test.3120425546 |
| 90.55 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.591456469 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.3851685320 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.167615149 |
| /workspace/coverage/default/10.prim_esc_test.2726186194 |
| /workspace/coverage/default/11.prim_esc_test.3918332700 |
| /workspace/coverage/default/13.prim_esc_test.1661583586 |
| /workspace/coverage/default/14.prim_esc_test.2558300343 |
| /workspace/coverage/default/16.prim_esc_test.3504498767 |
| /workspace/coverage/default/17.prim_esc_test.1663206353 |
| /workspace/coverage/default/18.prim_esc_test.2640506510 |
| /workspace/coverage/default/19.prim_esc_test.1347283596 |
| /workspace/coverage/default/2.prim_esc_test.3641853979 |
| /workspace/coverage/default/4.prim_esc_test.3338893286 |
| /workspace/coverage/default/6.prim_esc_test.843398582 |
| /workspace/coverage/default/8.prim_esc_test.4137314354 |
| /workspace/coverage/default/9.prim_esc_test.1415144229 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_esc_test.1663206353 | Jun 10 04:42:23 PM PDT 24 | Jun 10 04:42:24 PM PDT 24 | 5536212 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.843398582 | Jun 10 04:42:30 PM PDT 24 | Jun 10 04:42:31 PM PDT 24 | 4856731 ps | ||
| T3 | /workspace/coverage/default/9.prim_esc_test.1415144229 | Jun 10 04:42:19 PM PDT 24 | Jun 10 04:42:21 PM PDT 24 | 4381456 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.3504498767 | Jun 10 04:42:21 PM PDT 24 | Jun 10 04:42:22 PM PDT 24 | 4387977 ps | ||
| T4 | /workspace/coverage/default/10.prim_esc_test.2726186194 | Jun 10 04:42:34 PM PDT 24 | Jun 10 04:42:35 PM PDT 24 | 4794550 ps | ||
| T5 | /workspace/coverage/default/5.prim_esc_test.3120425546 | Jun 10 04:42:17 PM PDT 24 | Jun 10 04:42:20 PM PDT 24 | 5356047 ps | ||
| T6 | /workspace/coverage/default/2.prim_esc_test.3641853979 | Jun 10 04:42:17 PM PDT 24 | Jun 10 04:42:20 PM PDT 24 | 4812406 ps | ||
| T10 | /workspace/coverage/default/0.prim_esc_test.591456469 | Jun 10 04:42:18 PM PDT 24 | Jun 10 04:42:20 PM PDT 24 | 4586257 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.513992788 | Jun 10 04:42:32 PM PDT 24 | Jun 10 04:42:33 PM PDT 24 | 4401681 ps | ||
| T13 | /workspace/coverage/default/7.prim_esc_test.3851685320 | Jun 10 04:42:18 PM PDT 24 | Jun 10 04:42:21 PM PDT 24 | 5456559 ps | ||
| T14 | /workspace/coverage/default/13.prim_esc_test.1661583586 | Jun 10 04:42:32 PM PDT 24 | Jun 10 04:42:33 PM PDT 24 | 4688012 ps | ||
| T16 | /workspace/coverage/default/1.prim_esc_test.167615149 | Jun 10 04:42:29 PM PDT 24 | Jun 10 04:42:30 PM PDT 24 | 4703895 ps | ||
| T9 | /workspace/coverage/default/19.prim_esc_test.1347283596 | Jun 10 04:42:38 PM PDT 24 | Jun 10 04:42:39 PM PDT 24 | 4474018 ps | ||
| T17 | /workspace/coverage/default/11.prim_esc_test.3918332700 | Jun 10 04:42:20 PM PDT 24 | Jun 10 04:42:22 PM PDT 24 | 4680799 ps | ||
| T18 | /workspace/coverage/default/14.prim_esc_test.2558300343 | Jun 10 04:42:21 PM PDT 24 | Jun 10 04:42:22 PM PDT 24 | 4277458 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.3338893286 | Jun 10 04:42:18 PM PDT 24 | Jun 10 04:42:21 PM PDT 24 | 4957242 ps | ||
| T15 | /workspace/coverage/default/8.prim_esc_test.4137314354 | Jun 10 04:42:37 PM PDT 24 | Jun 10 04:42:38 PM PDT 24 | 5027652 ps | ||
| T11 | /workspace/coverage/default/18.prim_esc_test.2640506510 | Jun 10 04:42:33 PM PDT 24 | Jun 10 04:42:34 PM PDT 24 | 5350983 ps | ||
| T12 | /workspace/coverage/default/12.prim_esc_test.152416681 | Jun 10 04:42:20 PM PDT 24 | Jun 10 04:42:22 PM PDT 24 | 5112208 ps | ||
| T20 | /workspace/coverage/default/15.prim_esc_test.3515044254 | Jun 10 04:42:34 PM PDT 24 | Jun 10 04:42:35 PM PDT 24 | 4927805 ps |
| Test location | /workspace/coverage/default/3.prim_esc_test.513992788 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4401681 ps |
| CPU time | 0.38 seconds |
| Started | Jun 10 04:42:32 PM PDT 24 |
| Finished | Jun 10 04:42:33 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-9c0c081d-0f6c-495f-b9c6-98e9f3abea11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513992788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.513992788 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3515044254 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4927805 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:34 PM PDT 24 |
| Finished | Jun 10 04:42:35 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-147b15ef-e5a3-4042-97c3-7ab5a33a8521 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515044254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3515044254 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.152416681 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5112208 ps |
| CPU time | 0.38 seconds |
| Started | Jun 10 04:42:20 PM PDT 24 |
| Finished | Jun 10 04:42:22 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-34f01a01-d500-4997-bb56-2ff609177d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152416681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.152416681 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3120425546 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5356047 ps |
| CPU time | 0.39 seconds |
| Started | Jun 10 04:42:17 PM PDT 24 |
| Finished | Jun 10 04:42:20 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-d411492e-137a-4c44-a0fc-413888db477f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120425546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3120425546 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.591456469 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4586257 ps |
| CPU time | 0.42 seconds |
| Started | Jun 10 04:42:18 PM PDT 24 |
| Finished | Jun 10 04:42:20 PM PDT 24 |
| Peak memory | 145988 kb |
| Host | smart-f2e45552-bb45-4337-b156-232363d1626b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591456469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.591456469 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3851685320 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5456559 ps |
| CPU time | 0.4 seconds |
| Started | Jun 10 04:42:18 PM PDT 24 |
| Finished | Jun 10 04:42:21 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-6ea08877-937b-4885-8afe-52cce7dc910a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3851685320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3851685320 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.167615149 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4703895 ps |
| CPU time | 0.36 seconds |
| Started | Jun 10 04:42:29 PM PDT 24 |
| Finished | Jun 10 04:42:30 PM PDT 24 |
| Peak memory | 145944 kb |
| Host | smart-081ac51f-b4e4-404f-a205-7a1b12a4d022 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167615149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.167615149 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2726186194 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4794550 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:34 PM PDT 24 |
| Finished | Jun 10 04:42:35 PM PDT 24 |
| Peak memory | 146048 kb |
| Host | smart-14d5d28d-2924-4576-ac9c-e580c2fe3613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726186194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2726186194 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3918332700 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4680799 ps |
| CPU time | 0.36 seconds |
| Started | Jun 10 04:42:20 PM PDT 24 |
| Finished | Jun 10 04:42:22 PM PDT 24 |
| Peak memory | 146156 kb |
| Host | smart-968ff16f-c67a-4989-9236-dc50a212368f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918332700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3918332700 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1661583586 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4688012 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:32 PM PDT 24 |
| Finished | Jun 10 04:42:33 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-2e833a15-10a9-4096-bfc6-5c0f94004f9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661583586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1661583586 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2558300343 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4277458 ps |
| CPU time | 0.38 seconds |
| Started | Jun 10 04:42:21 PM PDT 24 |
| Finished | Jun 10 04:42:22 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-9aa82ada-466b-45f2-b1bf-afc19ae31ea2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558300343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2558300343 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3504498767 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4387977 ps |
| CPU time | 0.4 seconds |
| Started | Jun 10 04:42:21 PM PDT 24 |
| Finished | Jun 10 04:42:22 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-3773faa5-11ca-479e-a91c-78c599d5f42f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504498767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3504498767 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1663206353 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5536212 ps |
| CPU time | 0.38 seconds |
| Started | Jun 10 04:42:23 PM PDT 24 |
| Finished | Jun 10 04:42:24 PM PDT 24 |
| Peak memory | 146048 kb |
| Host | smart-adb469f9-f855-49d9-ab31-e1e33a8eadf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663206353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1663206353 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2640506510 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5350983 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:33 PM PDT 24 |
| Finished | Jun 10 04:42:34 PM PDT 24 |
| Peak memory | 146048 kb |
| Host | smart-32fa8755-def3-48a7-9c60-fe61984b684b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640506510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2640506510 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1347283596 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4474018 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:38 PM PDT 24 |
| Finished | Jun 10 04:42:39 PM PDT 24 |
| Peak memory | 145968 kb |
| Host | smart-def6ed08-07f1-4358-afde-7f5ddee37b78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347283596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1347283596 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3641853979 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4812406 ps |
| CPU time | 0.45 seconds |
| Started | Jun 10 04:42:17 PM PDT 24 |
| Finished | Jun 10 04:42:20 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-ec008930-fc20-4881-afef-792813c9d77e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641853979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3641853979 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3338893286 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4957242 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:18 PM PDT 24 |
| Finished | Jun 10 04:42:21 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-a663f154-68ba-4bb2-a80f-565ca870fc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338893286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3338893286 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.843398582 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4856731 ps |
| CPU time | 0.37 seconds |
| Started | Jun 10 04:42:30 PM PDT 24 |
| Finished | Jun 10 04:42:31 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-cd89db45-274a-45f7-94c4-665b3d104aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843398582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.843398582 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.4137314354 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5027652 ps |
| CPU time | 0.38 seconds |
| Started | Jun 10 04:42:37 PM PDT 24 |
| Finished | Jun 10 04:42:38 PM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-f549732a-8ba7-4fe3-b551-47334ac5871a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137314354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.4137314354 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1415144229 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4381456 ps |
| CPU time | 0.38 seconds |
| Started | Jun 10 04:42:19 PM PDT 24 |
| Finished | Jun 10 04:42:21 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-34b2f857-ece0-472d-bb6c-3fca6cf7f3ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415144229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1415144229 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |