| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.53 | 86.53 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/10.prim_esc_test.3246855973 |
| 88.27 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.3083222541 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.2412460623 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.3660535406 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1970039680 |
| /workspace/coverage/default/11.prim_esc_test.2685676535 |
| /workspace/coverage/default/12.prim_esc_test.932526706 |
| /workspace/coverage/default/13.prim_esc_test.738846634 |
| /workspace/coverage/default/14.prim_esc_test.477443993 |
| /workspace/coverage/default/15.prim_esc_test.361613186 |
| /workspace/coverage/default/17.prim_esc_test.1771254746 |
| /workspace/coverage/default/18.prim_esc_test.4282837568 |
| /workspace/coverage/default/19.prim_esc_test.618051579 |
| /workspace/coverage/default/2.prim_esc_test.599193883 |
| /workspace/coverage/default/3.prim_esc_test.1867671613 |
| /workspace/coverage/default/5.prim_esc_test.1246015123 |
| /workspace/coverage/default/6.prim_esc_test.625185675 |
| /workspace/coverage/default/7.prim_esc_test.3872230032 |
| /workspace/coverage/default/8.prim_esc_test.468104558 |
| /workspace/coverage/default/9.prim_esc_test.3601652887 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_esc_test.1970039680 | Jun 11 03:24:46 PM PDT 24 | Jun 11 03:24:48 PM PDT 24 | 5010394 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.3083222541 | Jun 11 03:24:46 PM PDT 24 | Jun 11 03:24:48 PM PDT 24 | 5052754 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.3246855973 | Jun 11 03:24:46 PM PDT 24 | Jun 11 03:24:48 PM PDT 24 | 5294373 ps | ||
| T4 | /workspace/coverage/default/8.prim_esc_test.468104558 | Jun 11 03:24:49 PM PDT 24 | Jun 11 03:24:52 PM PDT 24 | 5140640 ps | ||
| T10 | /workspace/coverage/default/19.prim_esc_test.618051579 | Jun 11 03:24:54 PM PDT 24 | Jun 11 03:24:56 PM PDT 24 | 4947270 ps | ||
| T5 | /workspace/coverage/default/4.prim_esc_test.2412460623 | Jun 11 03:24:46 PM PDT 24 | Jun 11 03:24:48 PM PDT 24 | 4947478 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.361613186 | Jun 11 03:24:53 PM PDT 24 | Jun 11 03:24:55 PM PDT 24 | 5209369 ps | ||
| T16 | /workspace/coverage/default/2.prim_esc_test.599193883 | Jun 11 03:24:48 PM PDT 24 | Jun 11 03:24:51 PM PDT 24 | 4919023 ps | ||
| T17 | /workspace/coverage/default/6.prim_esc_test.625185675 | Jun 11 03:24:48 PM PDT 24 | Jun 11 03:24:50 PM PDT 24 | 5079161 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.1867671613 | Jun 11 03:24:48 PM PDT 24 | Jun 11 03:24:50 PM PDT 24 | 4707976 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.932526706 | Jun 11 03:24:54 PM PDT 24 | Jun 11 03:24:56 PM PDT 24 | 4752603 ps | ||
| T18 | /workspace/coverage/default/11.prim_esc_test.2685676535 | Jun 11 03:24:45 PM PDT 24 | Jun 11 03:24:46 PM PDT 24 | 4822567 ps | ||
| T13 | /workspace/coverage/default/5.prim_esc_test.1246015123 | Jun 11 03:24:47 PM PDT 24 | Jun 11 03:24:49 PM PDT 24 | 5048596 ps | ||
| T14 | /workspace/coverage/default/18.prim_esc_test.4282837568 | Jun 11 03:24:54 PM PDT 24 | Jun 11 03:24:56 PM PDT 24 | 5244524 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.1771254746 | Jun 11 03:24:58 PM PDT 24 | Jun 11 03:25:00 PM PDT 24 | 4522247 ps | ||
| T19 | /workspace/coverage/default/7.prim_esc_test.3872230032 | Jun 11 03:24:48 PM PDT 24 | Jun 11 03:24:50 PM PDT 24 | 4534417 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.3601652887 | Jun 11 03:24:45 PM PDT 24 | Jun 11 03:24:47 PM PDT 24 | 5112389 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.3660535406 | Jun 11 03:24:54 PM PDT 24 | Jun 11 03:24:57 PM PDT 24 | 4562653 ps | ||
| T12 | /workspace/coverage/default/13.prim_esc_test.738846634 | Jun 11 03:24:53 PM PDT 24 | Jun 11 03:24:54 PM PDT 24 | 4631150 ps | ||
| T9 | /workspace/coverage/default/14.prim_esc_test.477443993 | Jun 11 03:24:54 PM PDT 24 | Jun 11 03:24:56 PM PDT 24 | 5260061 ps |
| Test location | /workspace/coverage/default/10.prim_esc_test.3246855973 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5294373 ps |
| CPU time | 0.37 seconds |
| Started | Jun 11 03:24:46 PM PDT 24 |
| Finished | Jun 11 03:24:48 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-34d2bf49-695f-43e2-be77-5a130aaf86f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246855973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3246855973 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3083222541 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5052754 ps |
| CPU time | 0.37 seconds |
| Started | Jun 11 03:24:46 PM PDT 24 |
| Finished | Jun 11 03:24:48 PM PDT 24 |
| Peak memory | 146096 kb |
| Host | smart-ec759aa6-eac8-432a-a186-ee2f81c0826b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083222541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3083222541 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2412460623 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4947478 ps |
| CPU time | 0.37 seconds |
| Started | Jun 11 03:24:46 PM PDT 24 |
| Finished | Jun 11 03:24:48 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-dbef066c-3ef8-4427-87a5-6a548784e529 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412460623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2412460623 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3660535406 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4562653 ps |
| CPU time | 0.41 seconds |
| Started | Jun 11 03:24:54 PM PDT 24 |
| Finished | Jun 11 03:24:57 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-0d7e346a-52f4-4b1a-bded-f1c3c588b3c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660535406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3660535406 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1970039680 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5010394 ps |
| CPU time | 0.37 seconds |
| Started | Jun 11 03:24:46 PM PDT 24 |
| Finished | Jun 11 03:24:48 PM PDT 24 |
| Peak memory | 146116 kb |
| Host | smart-088225dc-943b-4538-9835-0d7332e05145 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970039680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1970039680 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2685676535 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4822567 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:45 PM PDT 24 |
| Finished | Jun 11 03:24:46 PM PDT 24 |
| Peak memory | 146240 kb |
| Host | smart-5db757eb-4622-4b2b-a2c0-4e9896a4f5a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685676535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2685676535 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.932526706 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4752603 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:54 PM PDT 24 |
| Finished | Jun 11 03:24:56 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-19aae35e-0ab0-4205-be84-261d399a7bb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932526706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.932526706 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.738846634 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4631150 ps |
| CPU time | 0.4 seconds |
| Started | Jun 11 03:24:53 PM PDT 24 |
| Finished | Jun 11 03:24:54 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-376dfa9c-e874-44b2-b662-6b74e3389338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738846634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.738846634 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.477443993 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5260061 ps |
| CPU time | 0.38 seconds |
| Started | Jun 11 03:24:54 PM PDT 24 |
| Finished | Jun 11 03:24:56 PM PDT 24 |
| Peak memory | 146068 kb |
| Host | smart-9235db75-bcd2-43c4-82ac-4e153d4b487e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477443993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.477443993 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.361613186 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5209369 ps |
| CPU time | 0.38 seconds |
| Started | Jun 11 03:24:53 PM PDT 24 |
| Finished | Jun 11 03:24:55 PM PDT 24 |
| Peak memory | 146176 kb |
| Host | smart-79825c31-3885-48d4-a6e3-bda091cd021e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361613186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.361613186 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1771254746 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4522247 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:58 PM PDT 24 |
| Finished | Jun 11 03:25:00 PM PDT 24 |
| Peak memory | 146236 kb |
| Host | smart-ba2b1bec-2cc1-4fc3-b30f-3a6b02e2b6e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771254746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1771254746 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.4282837568 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5244524 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:54 PM PDT 24 |
| Finished | Jun 11 03:24:56 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-31fc2997-d4ce-4902-b335-e243d84921bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282837568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.4282837568 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.618051579 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4947270 ps |
| CPU time | 0.37 seconds |
| Started | Jun 11 03:24:54 PM PDT 24 |
| Finished | Jun 11 03:24:56 PM PDT 24 |
| Peak memory | 146184 kb |
| Host | smart-c2afe452-8da3-4a5b-bb9e-e18eb8071a09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618051579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.618051579 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.599193883 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4919023 ps |
| CPU time | 0.37 seconds |
| Started | Jun 11 03:24:48 PM PDT 24 |
| Finished | Jun 11 03:24:51 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-7cee2114-c138-426f-9616-25a27c26e7ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599193883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.599193883 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1867671613 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4707976 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:48 PM PDT 24 |
| Finished | Jun 11 03:24:50 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-6056c935-0975-4b52-bdcd-7779a992c704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867671613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1867671613 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1246015123 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5048596 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:47 PM PDT 24 |
| Finished | Jun 11 03:24:49 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-28197e7d-600a-4d91-a51f-77c166be7bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246015123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1246015123 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.625185675 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5079161 ps |
| CPU time | 0.38 seconds |
| Started | Jun 11 03:24:48 PM PDT 24 |
| Finished | Jun 11 03:24:50 PM PDT 24 |
| Peak memory | 146192 kb |
| Host | smart-d60bef13-dfd3-42ab-b47d-83d75a1d03d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625185675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.625185675 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3872230032 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4534417 ps |
| CPU time | 0.41 seconds |
| Started | Jun 11 03:24:48 PM PDT 24 |
| Finished | Jun 11 03:24:50 PM PDT 24 |
| Peak memory | 146104 kb |
| Host | smart-71fcb861-5020-470c-ab3e-e12232d5374e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872230032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3872230032 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.468104558 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5140640 ps |
| CPU time | 0.38 seconds |
| Started | Jun 11 03:24:49 PM PDT 24 |
| Finished | Jun 11 03:24:52 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-c5db1774-e211-4917-9b66-61035b96d0c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468104558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.468104558 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3601652887 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5112389 ps |
| CPU time | 0.39 seconds |
| Started | Jun 11 03:24:45 PM PDT 24 |
| Finished | Jun 11 03:24:47 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-8f42d776-5493-49f2-9467-8860308626b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601652887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3601652887 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |