Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.94 85.94 92.38 92.38 85.37 85.37 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/13.prim_esc_test.3328265444
88.27 2.33 93.33 0.95 85.37 0.00 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.2615181750
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/12.prim_esc_test.29910444
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/16.prim_esc_test.1199147601

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.104822719
/workspace/coverage/default/1.prim_esc_test.1913947587
/workspace/coverage/default/10.prim_esc_test.549469889
/workspace/coverage/default/14.prim_esc_test.1723189904
/workspace/coverage/default/15.prim_esc_test.1298078043
/workspace/coverage/default/17.prim_esc_test.3613830907
/workspace/coverage/default/18.prim_esc_test.3392434817
/workspace/coverage/default/19.prim_esc_test.696086450
/workspace/coverage/default/2.prim_esc_test.3428135172
/workspace/coverage/default/3.prim_esc_test.762722232
/workspace/coverage/default/4.prim_esc_test.1998098133
/workspace/coverage/default/5.prim_esc_test.3422019289
/workspace/coverage/default/6.prim_esc_test.3412914441
/workspace/coverage/default/7.prim_esc_test.3731314747
/workspace/coverage/default/8.prim_esc_test.208366312
/workspace/coverage/default/9.prim_esc_test.1554028274



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_esc_test.29910444 Jun 13 01:52:18 PM PDT 24 Jun 13 01:52:19 PM PDT 24 4526052 ps
T2 /workspace/coverage/default/7.prim_esc_test.3731314747 Jun 13 01:52:17 PM PDT 24 Jun 13 01:52:19 PM PDT 24 4603009 ps
T3 /workspace/coverage/default/1.prim_esc_test.1913947587 Jun 13 01:52:17 PM PDT 24 Jun 13 01:52:19 PM PDT 24 5008226 ps
T7 /workspace/coverage/default/15.prim_esc_test.1298078043 Jun 13 01:52:20 PM PDT 24 Jun 13 01:52:22 PM PDT 24 4459381 ps
T4 /workspace/coverage/default/4.prim_esc_test.1998098133 Jun 13 01:52:13 PM PDT 24 Jun 13 01:52:16 PM PDT 24 5019086 ps
T6 /workspace/coverage/default/17.prim_esc_test.3613830907 Jun 13 01:52:19 PM PDT 24 Jun 13 01:52:22 PM PDT 24 4761783 ps
T14 /workspace/coverage/default/19.prim_esc_test.696086450 Jun 13 01:52:18 PM PDT 24 Jun 13 01:52:21 PM PDT 24 5093020 ps
T15 /workspace/coverage/default/18.prim_esc_test.3392434817 Jun 13 01:52:21 PM PDT 24 Jun 13 01:52:23 PM PDT 24 4259681 ps
T5 /workspace/coverage/default/13.prim_esc_test.3328265444 Jun 13 01:52:19 PM PDT 24 Jun 13 01:52:22 PM PDT 24 4725137 ps
T12 /workspace/coverage/default/3.prim_esc_test.762722232 Jun 13 01:52:16 PM PDT 24 Jun 13 01:52:17 PM PDT 24 5102739 ps
T10 /workspace/coverage/default/2.prim_esc_test.3428135172 Jun 13 01:52:18 PM PDT 24 Jun 13 01:52:19 PM PDT 24 4322457 ps
T16 /workspace/coverage/default/10.prim_esc_test.549469889 Jun 13 01:52:12 PM PDT 24 Jun 13 01:52:13 PM PDT 24 5069637 ps
T17 /workspace/coverage/default/5.prim_esc_test.3422019289 Jun 13 01:52:18 PM PDT 24 Jun 13 01:52:20 PM PDT 24 4901304 ps
T18 /workspace/coverage/default/6.prim_esc_test.3412914441 Jun 13 01:52:13 PM PDT 24 Jun 13 01:52:16 PM PDT 24 4619426 ps
T8 /workspace/coverage/default/14.prim_esc_test.1723189904 Jun 13 01:52:22 PM PDT 24 Jun 13 01:52:24 PM PDT 24 5200244 ps
T9 /workspace/coverage/default/11.prim_esc_test.2615181750 Jun 13 01:52:12 PM PDT 24 Jun 13 01:52:13 PM PDT 24 4789436 ps
T13 /workspace/coverage/default/0.prim_esc_test.104822719 Jun 13 01:52:14 PM PDT 24 Jun 13 01:52:16 PM PDT 24 4577387 ps
T19 /workspace/coverage/default/8.prim_esc_test.208366312 Jun 13 01:52:22 PM PDT 24 Jun 13 01:52:24 PM PDT 24 5017720 ps
T20 /workspace/coverage/default/9.prim_esc_test.1554028274 Jun 13 01:52:16 PM PDT 24 Jun 13 01:52:18 PM PDT 24 4444607 ps
T11 /workspace/coverage/default/16.prim_esc_test.1199147601 Jun 13 01:52:18 PM PDT 24 Jun 13 01:52:21 PM PDT 24 5551185 ps

Test location /workspace/coverage/default/13.prim_esc_test.3328265444
Short name T5
Test name
Test status
Simulation time 4725137 ps
CPU time 0.41 seconds
Started Jun 13 01:52:19 PM PDT 24
Finished Jun 13 01:52:22 PM PDT 24
Peak memory 146204 kb
Host smart-f5179b5b-b010-4cf4-8ec7-643226d724c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328265444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3328265444
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2615181750
Short name T9
Test name
Test status
Simulation time 4789436 ps
CPU time 0.36 seconds
Started Jun 13 01:52:12 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 146160 kb
Host smart-347cadae-8e61-4bce-b20b-a7dadbe22b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615181750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2615181750
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.29910444
Short name T1
Test name
Test status
Simulation time 4526052 ps
CPU time 0.39 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:19 PM PDT 24
Peak memory 146188 kb
Host smart-224dab98-f0ab-4e74-8a8c-3f21b78e8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29910444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.29910444
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1199147601
Short name T11
Test name
Test status
Simulation time 5551185 ps
CPU time 0.4 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:21 PM PDT 24
Peak memory 146188 kb
Host smart-c459c776-5a20-4bda-af7a-88ab91be2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199147601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1199147601
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.104822719
Short name T13
Test name
Test status
Simulation time 4577387 ps
CPU time 0.37 seconds
Started Jun 13 01:52:14 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 146208 kb
Host smart-39e86224-a5a4-419b-8005-e19686de7b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104822719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.104822719
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.1913947587
Short name T3
Test name
Test status
Simulation time 5008226 ps
CPU time 0.39 seconds
Started Jun 13 01:52:17 PM PDT 24
Finished Jun 13 01:52:19 PM PDT 24
Peak memory 146200 kb
Host smart-14d7df0a-aaaa-4bed-98ce-d91f3e0b562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913947587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1913947587
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.549469889
Short name T16
Test name
Test status
Simulation time 5069637 ps
CPU time 0.38 seconds
Started Jun 13 01:52:12 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 146244 kb
Host smart-58e1c766-f016-4475-a8d8-39a37a8281a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549469889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.549469889
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1723189904
Short name T8
Test name
Test status
Simulation time 5200244 ps
CPU time 0.37 seconds
Started Jun 13 01:52:22 PM PDT 24
Finished Jun 13 01:52:24 PM PDT 24
Peak memory 146316 kb
Host smart-09c9d044-1a07-4029-a28d-e616f0392bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723189904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1723189904
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1298078043
Short name T7
Test name
Test status
Simulation time 4459381 ps
CPU time 0.38 seconds
Started Jun 13 01:52:20 PM PDT 24
Finished Jun 13 01:52:22 PM PDT 24
Peak memory 146244 kb
Host smart-2f354f8a-e401-46d5-b502-3eca17b63fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298078043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1298078043
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3613830907
Short name T6
Test name
Test status
Simulation time 4761783 ps
CPU time 0.37 seconds
Started Jun 13 01:52:19 PM PDT 24
Finished Jun 13 01:52:22 PM PDT 24
Peak memory 146196 kb
Host smart-2b8f6801-84fa-43e6-bb47-bcf736162e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613830907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3613830907
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3392434817
Short name T15
Test name
Test status
Simulation time 4259681 ps
CPU time 0.39 seconds
Started Jun 13 01:52:21 PM PDT 24
Finished Jun 13 01:52:23 PM PDT 24
Peak memory 146196 kb
Host smart-eb4a61f8-70c3-4cfa-86ec-998821380d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392434817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3392434817
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.696086450
Short name T14
Test name
Test status
Simulation time 5093020 ps
CPU time 0.39 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:21 PM PDT 24
Peak memory 146192 kb
Host smart-4c4d0d66-e9d2-49f6-9812-903a31b9251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696086450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.696086450
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3428135172
Short name T10
Test name
Test status
Simulation time 4322457 ps
CPU time 0.4 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:19 PM PDT 24
Peak memory 146200 kb
Host smart-b643f743-f29c-4bed-86e0-90e08b782020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428135172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3428135172
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.762722232
Short name T12
Test name
Test status
Simulation time 5102739 ps
CPU time 0.37 seconds
Started Jun 13 01:52:16 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 146196 kb
Host smart-adf2d783-bfa9-4785-843a-9dd54c515a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762722232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.762722232
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.1998098133
Short name T4
Test name
Test status
Simulation time 5019086 ps
CPU time 0.38 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 146172 kb
Host smart-4fa01c08-3619-49c9-bdcb-222def0beb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998098133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1998098133
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3422019289
Short name T17
Test name
Test status
Simulation time 4901304 ps
CPU time 0.41 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:20 PM PDT 24
Peak memory 146192 kb
Host smart-264ba467-b2ac-4074-913e-b0d9393f9828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422019289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3422019289
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.3412914441
Short name T18
Test name
Test status
Simulation time 4619426 ps
CPU time 0.42 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 146196 kb
Host smart-e3b473e0-bc32-4555-b39a-d07fed0f558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412914441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3412914441
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3731314747
Short name T2
Test name
Test status
Simulation time 4603009 ps
CPU time 0.39 seconds
Started Jun 13 01:52:17 PM PDT 24
Finished Jun 13 01:52:19 PM PDT 24
Peak memory 146200 kb
Host smart-ceb17451-da73-4f88-8123-ceb86d0f45d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731314747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3731314747
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.208366312
Short name T19
Test name
Test status
Simulation time 5017720 ps
CPU time 0.39 seconds
Started Jun 13 01:52:22 PM PDT 24
Finished Jun 13 01:52:24 PM PDT 24
Peak memory 146188 kb
Host smart-86123717-4f26-4556-bfd9-ed2f49dc64cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208366312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.208366312
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.1554028274
Short name T20
Test name
Test status
Simulation time 4444607 ps
CPU time 0.39 seconds
Started Jun 13 01:52:16 PM PDT 24
Finished Jun 13 01:52:18 PM PDT 24
Peak memory 146200 kb
Host smart-fef27e13-1dc5-4596-bb2d-e83bdbfdafc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554028274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1554028274
Directory /workspace/9.prim_esc_test/latest
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