Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.94 85.94 92.38 92.38 85.37 85.37 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/15.prim_esc_test.1311674537
88.27 2.33 93.33 0.95 85.37 0.00 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/4.prim_esc_test.2162058176
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/18.prim_esc_test.2300970736
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.882249593

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.2296949543
/workspace/coverage/default/1.prim_esc_test.4142656772
/workspace/coverage/default/10.prim_esc_test.2919902911
/workspace/coverage/default/11.prim_esc_test.2237506443
/workspace/coverage/default/12.prim_esc_test.888139970
/workspace/coverage/default/14.prim_esc_test.455407875
/workspace/coverage/default/16.prim_esc_test.1495960419
/workspace/coverage/default/17.prim_esc_test.2853627819
/workspace/coverage/default/19.prim_esc_test.1023727963
/workspace/coverage/default/2.prim_esc_test.2901535940
/workspace/coverage/default/3.prim_esc_test.2548121546
/workspace/coverage/default/5.prim_esc_test.3888760342
/workspace/coverage/default/6.prim_esc_test.3558760824
/workspace/coverage/default/7.prim_esc_test.3878761387
/workspace/coverage/default/8.prim_esc_test.558917488
/workspace/coverage/default/9.prim_esc_test.2788919764



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_esc_test.2300970736 Jun 21 04:22:13 PM PDT 24 Jun 21 04:22:14 PM PDT 24 4759905 ps
T2 /workspace/coverage/default/11.prim_esc_test.2237506443 Jun 21 04:22:15 PM PDT 24 Jun 21 04:22:17 PM PDT 24 5634654 ps
T3 /workspace/coverage/default/6.prim_esc_test.3558760824 Jun 21 04:22:00 PM PDT 24 Jun 21 04:22:02 PM PDT 24 4952332 ps
T6 /workspace/coverage/default/8.prim_esc_test.558917488 Jun 21 04:22:12 PM PDT 24 Jun 21 04:22:14 PM PDT 24 4897609 ps
T4 /workspace/coverage/default/5.prim_esc_test.3888760342 Jun 21 04:22:13 PM PDT 24 Jun 21 04:22:14 PM PDT 24 4536885 ps
T8 /workspace/coverage/default/16.prim_esc_test.1495960419 Jun 21 04:22:02 PM PDT 24 Jun 21 04:22:04 PM PDT 24 4614638 ps
T5 /workspace/coverage/default/4.prim_esc_test.2162058176 Jun 21 04:22:15 PM PDT 24 Jun 21 04:22:16 PM PDT 24 4545283 ps
T11 /workspace/coverage/default/13.prim_esc_test.882249593 Jun 21 04:21:57 PM PDT 24 Jun 21 04:21:58 PM PDT 24 5241128 ps
T9 /workspace/coverage/default/15.prim_esc_test.1311674537 Jun 21 04:20:53 PM PDT 24 Jun 21 04:20:58 PM PDT 24 5176708 ps
T7 /workspace/coverage/default/19.prim_esc_test.1023727963 Jun 21 04:22:14 PM PDT 24 Jun 21 04:22:16 PM PDT 24 4718377 ps
T10 /workspace/coverage/default/0.prim_esc_test.2296949543 Jun 21 04:21:57 PM PDT 24 Jun 21 04:21:58 PM PDT 24 4818699 ps
T17 /workspace/coverage/default/3.prim_esc_test.2548121546 Jun 21 04:22:15 PM PDT 24 Jun 21 04:22:16 PM PDT 24 4734643 ps
T18 /workspace/coverage/default/10.prim_esc_test.2919902911 Jun 21 04:22:02 PM PDT 24 Jun 21 04:22:04 PM PDT 24 5189535 ps
T12 /workspace/coverage/default/14.prim_esc_test.455407875 Jun 21 04:22:15 PM PDT 24 Jun 21 04:22:17 PM PDT 24 4823592 ps
T15 /workspace/coverage/default/1.prim_esc_test.4142656772 Jun 21 04:20:53 PM PDT 24 Jun 21 04:20:57 PM PDT 24 4916162 ps
T14 /workspace/coverage/default/7.prim_esc_test.3878761387 Jun 21 04:22:00 PM PDT 24 Jun 21 04:22:02 PM PDT 24 4475217 ps
T19 /workspace/coverage/default/9.prim_esc_test.2788919764 Jun 21 04:22:12 PM PDT 24 Jun 21 04:22:13 PM PDT 24 4654652 ps
T13 /workspace/coverage/default/2.prim_esc_test.2901535940 Jun 21 04:22:12 PM PDT 24 Jun 21 04:22:13 PM PDT 24 4746398 ps
T16 /workspace/coverage/default/12.prim_esc_test.888139970 Jun 21 04:20:52 PM PDT 24 Jun 21 04:20:56 PM PDT 24 5199405 ps
T20 /workspace/coverage/default/17.prim_esc_test.2853627819 Jun 21 04:20:53 PM PDT 24 Jun 21 04:20:58 PM PDT 24 4392888 ps

Test location /workspace/coverage/default/15.prim_esc_test.1311674537
Short name T9
Test name
Test status
Simulation time 5176708 ps
CPU time 0.36 seconds
Started Jun 21 04:20:53 PM PDT 24
Finished Jun 21 04:20:58 PM PDT 24
Peak memory 145680 kb
Host smart-8a025fb2-9e47-49af-ae50-ffa643161fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311674537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1311674537
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2162058176
Short name T5
Test name
Test status
Simulation time 4545283 ps
CPU time 0.39 seconds
Started Jun 21 04:22:15 PM PDT 24
Finished Jun 21 04:22:16 PM PDT 24
Peak memory 145644 kb
Host smart-e6da6412-c1db-4736-ad5a-1200a493f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162058176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2162058176
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2300970736
Short name T1
Test name
Test status
Simulation time 4759905 ps
CPU time 0.37 seconds
Started Jun 21 04:22:13 PM PDT 24
Finished Jun 21 04:22:14 PM PDT 24
Peak memory 145708 kb
Host smart-93d0c63c-62b4-4c63-b40f-42506ebca5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300970736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2300970736
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.882249593
Short name T11
Test name
Test status
Simulation time 5241128 ps
CPU time 0.41 seconds
Started Jun 21 04:21:57 PM PDT 24
Finished Jun 21 04:21:58 PM PDT 24
Peak memory 145432 kb
Host smart-1af23147-7322-4f8c-97e7-714ac32db29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882249593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.882249593
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2296949543
Short name T10
Test name
Test status
Simulation time 4818699 ps
CPU time 0.4 seconds
Started Jun 21 04:21:57 PM PDT 24
Finished Jun 21 04:21:58 PM PDT 24
Peak memory 145412 kb
Host smart-afe025f8-55fb-4f01-9de5-06dfb59ebb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296949543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2296949543
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.4142656772
Short name T15
Test name
Test status
Simulation time 4916162 ps
CPU time 0.37 seconds
Started Jun 21 04:20:53 PM PDT 24
Finished Jun 21 04:20:57 PM PDT 24
Peak memory 145680 kb
Host smart-532b8938-c646-4a6c-9889-e1fc7b8bbf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142656772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4142656772
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2919902911
Short name T18
Test name
Test status
Simulation time 5189535 ps
CPU time 0.46 seconds
Started Jun 21 04:22:02 PM PDT 24
Finished Jun 21 04:22:04 PM PDT 24
Peak memory 145080 kb
Host smart-aa8e2cdd-116a-4ff1-99db-1130d70ae0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919902911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2919902911
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2237506443
Short name T2
Test name
Test status
Simulation time 5634654 ps
CPU time 0.39 seconds
Started Jun 21 04:22:15 PM PDT 24
Finished Jun 21 04:22:17 PM PDT 24
Peak memory 145752 kb
Host smart-bf703d40-1b4c-4be2-8ef3-bd749a621add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237506443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2237506443
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.888139970
Short name T16
Test name
Test status
Simulation time 5199405 ps
CPU time 0.37 seconds
Started Jun 21 04:20:52 PM PDT 24
Finished Jun 21 04:20:56 PM PDT 24
Peak memory 145620 kb
Host smart-e9fb3438-0230-4450-a7f2-281ce87d6bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888139970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.888139970
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.455407875
Short name T12
Test name
Test status
Simulation time 4823592 ps
CPU time 0.37 seconds
Started Jun 21 04:22:15 PM PDT 24
Finished Jun 21 04:22:17 PM PDT 24
Peak memory 145716 kb
Host smart-88e723bb-7c4b-4bc7-a0f8-5e4397c3a1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455407875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.455407875
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1495960419
Short name T8
Test name
Test status
Simulation time 4614638 ps
CPU time 0.39 seconds
Started Jun 21 04:22:02 PM PDT 24
Finished Jun 21 04:22:04 PM PDT 24
Peak memory 145920 kb
Host smart-330b551a-eeb2-4a13-a367-f49a96696327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495960419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1495960419
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2853627819
Short name T20
Test name
Test status
Simulation time 4392888 ps
CPU time 0.42 seconds
Started Jun 21 04:20:53 PM PDT 24
Finished Jun 21 04:20:58 PM PDT 24
Peak memory 145808 kb
Host smart-a90f80b8-dc8a-4857-bdf9-a46caf97f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853627819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2853627819
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1023727963
Short name T7
Test name
Test status
Simulation time 4718377 ps
CPU time 0.38 seconds
Started Jun 21 04:22:14 PM PDT 24
Finished Jun 21 04:22:16 PM PDT 24
Peak memory 145664 kb
Host smart-e80912fe-4269-4758-9302-15504edd4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023727963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1023727963
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2901535940
Short name T13
Test name
Test status
Simulation time 4746398 ps
CPU time 0.36 seconds
Started Jun 21 04:22:12 PM PDT 24
Finished Jun 21 04:22:13 PM PDT 24
Peak memory 145636 kb
Host smart-d325e445-8945-4029-b679-3e1a5eb2c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901535940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2901535940
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2548121546
Short name T17
Test name
Test status
Simulation time 4734643 ps
CPU time 0.38 seconds
Started Jun 21 04:22:15 PM PDT 24
Finished Jun 21 04:22:16 PM PDT 24
Peak memory 145660 kb
Host smart-35997c46-f896-4041-a6eb-85a59e0f4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548121546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2548121546
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3888760342
Short name T4
Test name
Test status
Simulation time 4536885 ps
CPU time 0.37 seconds
Started Jun 21 04:22:13 PM PDT 24
Finished Jun 21 04:22:14 PM PDT 24
Peak memory 145688 kb
Host smart-945fa4a2-22eb-4fd9-8bea-3aa738608d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888760342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3888760342
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.3558760824
Short name T3
Test name
Test status
Simulation time 4952332 ps
CPU time 0.45 seconds
Started Jun 21 04:22:00 PM PDT 24
Finished Jun 21 04:22:02 PM PDT 24
Peak memory 144328 kb
Host smart-9a9fa88a-6b37-4b13-8398-5680f64b8b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558760824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3558760824
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3878761387
Short name T14
Test name
Test status
Simulation time 4475217 ps
CPU time 0.45 seconds
Started Jun 21 04:22:00 PM PDT 24
Finished Jun 21 04:22:02 PM PDT 24
Peak memory 144780 kb
Host smart-923b2e2c-dc5f-44bc-9e8e-2e8fd1d8461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878761387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3878761387
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.558917488
Short name T6
Test name
Test status
Simulation time 4897609 ps
CPU time 0.36 seconds
Started Jun 21 04:22:12 PM PDT 24
Finished Jun 21 04:22:14 PM PDT 24
Peak memory 145636 kb
Host smart-fffd1863-752d-4ea7-9748-6271d43ea0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558917488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.558917488
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2788919764
Short name T19
Test name
Test status
Simulation time 4654652 ps
CPU time 0.38 seconds
Started Jun 21 04:22:12 PM PDT 24
Finished Jun 21 04:22:13 PM PDT 24
Peak memory 145636 kb
Host smart-515b1217-f997-407f-ae12-2dfb45c90df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788919764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2788919764
Directory /workspace/9.prim_esc_test/latest
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