| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.01 | 94.29 | 85.37 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.94 | 85.94 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/4.prim_esc_test.1342628832 |
| 87.67 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/5.prim_esc_test.2618922850 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.429152671 |
| 90.01 | 0.60 | 94.29 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3349933093 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2907769670 |
| /workspace/coverage/default/1.prim_esc_test.880408604 |
| /workspace/coverage/default/10.prim_esc_test.758591914 |
| /workspace/coverage/default/11.prim_esc_test.310030289 |
| /workspace/coverage/default/12.prim_esc_test.8191024 |
| /workspace/coverage/default/14.prim_esc_test.1614318049 |
| /workspace/coverage/default/15.prim_esc_test.3773745895 |
| /workspace/coverage/default/16.prim_esc_test.2979643563 |
| /workspace/coverage/default/17.prim_esc_test.919466615 |
| /workspace/coverage/default/18.prim_esc_test.3067633780 |
| /workspace/coverage/default/19.prim_esc_test.3888562415 |
| /workspace/coverage/default/2.prim_esc_test.4261956827 |
| /workspace/coverage/default/3.prim_esc_test.2268738075 |
| /workspace/coverage/default/6.prim_esc_test.328959731 |
| /workspace/coverage/default/8.prim_esc_test.2104194330 |
| /workspace/coverage/default/9.prim_esc_test.3880229233 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_esc_test.758591914 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:46 PM PDT 24 | 4504262 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.4261956827 | Jun 22 04:16:40 PM PDT 24 | Jun 22 04:16:42 PM PDT 24 | 5014859 ps | ||
| T3 | /workspace/coverage/default/4.prim_esc_test.1342628832 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 5024377 ps | ||
| T5 | /workspace/coverage/default/9.prim_esc_test.3880229233 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 5189706 ps | ||
| T4 | /workspace/coverage/default/8.prim_esc_test.2104194330 | Jun 22 04:16:51 PM PDT 24 | Jun 22 04:16:52 PM PDT 24 | 5339394 ps | ||
| T6 | /workspace/coverage/default/0.prim_esc_test.2907769670 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 4730609 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.3773745895 | Jun 22 04:17:48 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 5039412 ps | ||
| T16 | /workspace/coverage/default/1.prim_esc_test.880408604 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 4917063 ps | ||
| T9 | /workspace/coverage/default/12.prim_esc_test.8191024 | Jun 22 04:16:40 PM PDT 24 | Jun 22 04:16:42 PM PDT 24 | 4527584 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.429152671 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 4730485 ps | ||
| T11 | /workspace/coverage/default/5.prim_esc_test.2618922850 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 4816111 ps | ||
| T10 | /workspace/coverage/default/13.prim_esc_test.3349933093 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 4932735 ps | ||
| T15 | /workspace/coverage/default/3.prim_esc_test.2268738075 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 5288582 ps | ||
| T17 | /workspace/coverage/default/17.prim_esc_test.919466615 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 4415558 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.3067633780 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 4670252 ps | ||
| T18 | /workspace/coverage/default/14.prim_esc_test.1614318049 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 4577238 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.3888562415 | Jun 22 04:16:51 PM PDT 24 | Jun 22 04:16:52 PM PDT 24 | 4739899 ps | ||
| T20 | /workspace/coverage/default/16.prim_esc_test.2979643563 | Jun 22 04:18:04 PM PDT 24 | Jun 22 04:18:05 PM PDT 24 | 4719190 ps | ||
| T12 | /workspace/coverage/default/6.prim_esc_test.328959731 | Jun 22 04:18:04 PM PDT 24 | Jun 22 04:18:05 PM PDT 24 | 4856310 ps | ||
| T13 | /workspace/coverage/default/11.prim_esc_test.310030289 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 5013740 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.1342628832 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5024377 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-066d948e-e485-414d-8ae8-af2bbcb870ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342628832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1342628832 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2618922850 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4816111 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-3dd127a1-a817-4f3e-8851-91cf11fb496a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618922850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2618922850 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.429152671 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4730485 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-067112d9-1f02-4ea9-aa73-035bfcca462f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429152671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.429152671 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3349933093 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4932735 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-974408f8-603a-483d-821f-fb5d02f54ab8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349933093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3349933093 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2907769670 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4730609 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-ae9c6b27-1d53-4563-b8bb-7c14a6268a09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907769670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2907769670 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.880408604 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4917063 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-40a5f1ea-7acc-406a-a18b-3d863dbc1379 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880408604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.880408604 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.758591914 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4504262 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:46 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-afed87a5-3290-4001-b082-5590314135e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758591914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.758591914 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.310030289 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5013740 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-66e5eebd-800d-4a4f-8764-ae2bb8751e8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310030289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.310030289 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.8191024 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4527584 ps |
| CPU time | 0.49 seconds |
| Started | Jun 22 04:16:40 PM PDT 24 |
| Finished | Jun 22 04:16:42 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-5e1cd678-f5b8-49c4-9e7b-20efa99258ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8191024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.8191024 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1614318049 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4577238 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-60b2c07f-b495-4f3a-89f0-9b2658793e91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614318049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1614318049 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3773745895 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5039412 ps |
| CPU time | 0.43 seconds |
| Started | Jun 22 04:17:48 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 144528 kb |
| Host | smart-31b734a3-ab5d-4757-8d43-b8e106f660c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773745895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3773745895 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2979643563 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4719190 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:18:04 PM PDT 24 |
| Finished | Jun 22 04:18:05 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-78ed94ed-540d-403f-b477-906ca2000822 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979643563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2979643563 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.919466615 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4415558 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-eaab7a94-1018-4f2c-9c7c-c66916b7fbbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919466615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.919466615 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3067633780 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4670252 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-df521c39-09e1-426d-adf0-bebc8d8aa9ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067633780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3067633780 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3888562415 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4739899 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:51 PM PDT 24 |
| Finished | Jun 22 04:16:52 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-79a14171-af04-4d25-b287-8ce1c935672f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888562415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3888562415 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.4261956827 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5014859 ps |
| CPU time | 0.46 seconds |
| Started | Jun 22 04:16:40 PM PDT 24 |
| Finished | Jun 22 04:16:42 PM PDT 24 |
| Peak memory | 144732 kb |
| Host | smart-2efd8d76-e947-4201-b868-0614f41735a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261956827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4261956827 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2268738075 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5288582 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-a3cd9c64-7ac3-497c-a689-b7356cf3b194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268738075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2268738075 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.328959731 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4856310 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:18:04 PM PDT 24 |
| Finished | Jun 22 04:18:05 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-fe6ba61a-2459-4210-93b7-2c062ee519db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328959731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.328959731 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2104194330 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5339394 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:51 PM PDT 24 |
| Finished | Jun 22 04:16:52 PM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-d471b792-35ff-4052-b018-33f5dabd4fa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104194330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2104194330 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3880229233 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5189706 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-5ee43871-5d30-41f3-9cc3-832a7d9a70c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880229233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3880229233 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |