Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.31 85.31 92.38 92.38 78.05 78.05 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/14.prim_esc_test.257324078
88.05 2.74 93.33 0.95 80.49 2.44 100.00 0.00 89.29 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/3.prim_esc_test.636806739
90.01 1.95 94.29 0.95 85.37 4.88 100.00 0.00 92.86 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.2519598233
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/17.prim_esc_test.1145513647

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.3155705540
/workspace/coverage/default/1.prim_esc_test.2447146469
/workspace/coverage/default/11.prim_esc_test.1126846177
/workspace/coverage/default/12.prim_esc_test.3335491184
/workspace/coverage/default/13.prim_esc_test.2705950481
/workspace/coverage/default/15.prim_esc_test.1980821032
/workspace/coverage/default/16.prim_esc_test.1777356994
/workspace/coverage/default/18.prim_esc_test.716338429
/workspace/coverage/default/19.prim_esc_test.544048975
/workspace/coverage/default/2.prim_esc_test.1648230323
/workspace/coverage/default/4.prim_esc_test.1490820123
/workspace/coverage/default/5.prim_esc_test.188983410
/workspace/coverage/default/6.prim_esc_test.1972991566
/workspace/coverage/default/7.prim_esc_test.969757271
/workspace/coverage/default/8.prim_esc_test.1392456518
/workspace/coverage/default/9.prim_esc_test.3155034988



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.prim_esc_test.1648230323 Jun 23 04:19:31 PM PDT 24 Jun 23 04:19:32 PM PDT 24 5153525 ps
T2 /workspace/coverage/default/3.prim_esc_test.636806739 Jun 23 04:19:56 PM PDT 24 Jun 23 04:19:57 PM PDT 24 5000863 ps
T3 /workspace/coverage/default/14.prim_esc_test.257324078 Jun 23 04:30:36 PM PDT 24 Jun 23 04:30:37 PM PDT 24 4816111 ps
T7 /workspace/coverage/default/5.prim_esc_test.188983410 Jun 23 04:23:15 PM PDT 24 Jun 23 04:23:16 PM PDT 24 4823478 ps
T6 /workspace/coverage/default/11.prim_esc_test.1126846177 Jun 23 04:30:34 PM PDT 24 Jun 23 04:30:35 PM PDT 24 4467992 ps
T9 /workspace/coverage/default/15.prim_esc_test.1980821032 Jun 23 04:30:28 PM PDT 24 Jun 23 04:30:29 PM PDT 24 4615916 ps
T4 /workspace/coverage/default/10.prim_esc_test.2519598233 Jun 23 04:30:37 PM PDT 24 Jun 23 04:30:38 PM PDT 24 4381429 ps
T5 /workspace/coverage/default/19.prim_esc_test.544048975 Jun 23 04:30:53 PM PDT 24 Jun 23 04:30:54 PM PDT 24 4928854 ps
T12 /workspace/coverage/default/4.prim_esc_test.1490820123 Jun 23 04:22:51 PM PDT 24 Jun 23 04:22:52 PM PDT 24 4808623 ps
T10 /workspace/coverage/default/18.prim_esc_test.716338429 Jun 23 04:30:33 PM PDT 24 Jun 23 04:30:34 PM PDT 24 5031490 ps
T13 /workspace/coverage/default/1.prim_esc_test.2447146469 Jun 23 04:19:23 PM PDT 24 Jun 23 04:19:24 PM PDT 24 5246655 ps
T14 /workspace/coverage/default/16.prim_esc_test.1777356994 Jun 23 04:30:25 PM PDT 24 Jun 23 04:30:26 PM PDT 24 4926108 ps
T15 /workspace/coverage/default/6.prim_esc_test.1972991566 Jun 23 04:21:28 PM PDT 24 Jun 23 04:21:29 PM PDT 24 4327295 ps
T16 /workspace/coverage/default/13.prim_esc_test.2705950481 Jun 23 04:30:24 PM PDT 24 Jun 23 04:30:29 PM PDT 24 5876106 ps
T11 /workspace/coverage/default/12.prim_esc_test.3335491184 Jun 23 04:30:59 PM PDT 24 Jun 23 04:31:00 PM PDT 24 5112147 ps
T17 /workspace/coverage/default/8.prim_esc_test.1392456518 Jun 23 04:19:56 PM PDT 24 Jun 23 04:19:57 PM PDT 24 5115057 ps
T8 /workspace/coverage/default/17.prim_esc_test.1145513647 Jun 23 04:30:40 PM PDT 24 Jun 23 04:30:41 PM PDT 24 5383922 ps
T18 /workspace/coverage/default/9.prim_esc_test.3155034988 Jun 23 04:19:42 PM PDT 24 Jun 23 04:19:43 PM PDT 24 5145544 ps
T19 /workspace/coverage/default/7.prim_esc_test.969757271 Jun 23 04:20:12 PM PDT 24 Jun 23 04:20:13 PM PDT 24 5102029 ps
T20 /workspace/coverage/default/0.prim_esc_test.3155705540 Jun 23 04:23:17 PM PDT 24 Jun 23 04:23:18 PM PDT 24 4194685 ps

Test location /workspace/coverage/default/14.prim_esc_test.257324078
Short name T3
Test name
Test status
Simulation time 4816111 ps
CPU time 0.37 seconds
Started Jun 23 04:30:36 PM PDT 24
Finished Jun 23 04:30:37 PM PDT 24
Peak memory 146000 kb
Host smart-3d89ce9c-95ff-45d2-a9ed-b03baed0e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257324078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.257324078
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.636806739
Short name T2
Test name
Test status
Simulation time 5000863 ps
CPU time 0.39 seconds
Started Jun 23 04:19:56 PM PDT 24
Finished Jun 23 04:19:57 PM PDT 24
Peak memory 145684 kb
Host smart-e1826084-8b15-488b-a4b3-35aca28320a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636806739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.636806739
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2519598233
Short name T4
Test name
Test status
Simulation time 4381429 ps
CPU time 0.38 seconds
Started Jun 23 04:30:37 PM PDT 24
Finished Jun 23 04:30:38 PM PDT 24
Peak memory 146024 kb
Host smart-7802808a-c487-44f7-84a3-6b5738f4d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519598233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2519598233
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1145513647
Short name T8
Test name
Test status
Simulation time 5383922 ps
CPU time 0.38 seconds
Started Jun 23 04:30:40 PM PDT 24
Finished Jun 23 04:30:41 PM PDT 24
Peak memory 146040 kb
Host smart-e75158bc-8508-49b2-8705-f95dc09662db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145513647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1145513647
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3155705540
Short name T20
Test name
Test status
Simulation time 4194685 ps
CPU time 0.39 seconds
Started Jun 23 04:23:17 PM PDT 24
Finished Jun 23 04:23:18 PM PDT 24
Peak memory 146368 kb
Host smart-d646a6ea-6d54-4bf0-84ba-f68fab92e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155705540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3155705540
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.2447146469
Short name T13
Test name
Test status
Simulation time 5246655 ps
CPU time 0.5 seconds
Started Jun 23 04:19:23 PM PDT 24
Finished Jun 23 04:19:24 PM PDT 24
Peak memory 146384 kb
Host smart-8dca693b-ccbe-4df7-ab1c-92478ee060ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447146469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2447146469
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1126846177
Short name T6
Test name
Test status
Simulation time 4467992 ps
CPU time 0.38 seconds
Started Jun 23 04:30:34 PM PDT 24
Finished Jun 23 04:30:35 PM PDT 24
Peak memory 146032 kb
Host smart-67f3d840-d51f-468b-9517-5f9f8a14844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126846177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1126846177
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.3335491184
Short name T11
Test name
Test status
Simulation time 5112147 ps
CPU time 0.37 seconds
Started Jun 23 04:30:59 PM PDT 24
Finished Jun 23 04:31:00 PM PDT 24
Peak memory 146036 kb
Host smart-b232c791-f323-4ebc-a704-35b3009b3939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335491184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3335491184
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2705950481
Short name T16
Test name
Test status
Simulation time 5876106 ps
CPU time 0.38 seconds
Started Jun 23 04:30:24 PM PDT 24
Finished Jun 23 04:30:29 PM PDT 24
Peak memory 146036 kb
Host smart-4ad037bb-3376-4750-ae7a-8d2ee6ba444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705950481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2705950481
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1980821032
Short name T9
Test name
Test status
Simulation time 4615916 ps
CPU time 0.38 seconds
Started Jun 23 04:30:28 PM PDT 24
Finished Jun 23 04:30:29 PM PDT 24
Peak memory 146036 kb
Host smart-eac551bf-9534-4508-94cc-4588af01c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980821032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1980821032
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1777356994
Short name T14
Test name
Test status
Simulation time 4926108 ps
CPU time 0.39 seconds
Started Jun 23 04:30:25 PM PDT 24
Finished Jun 23 04:30:26 PM PDT 24
Peak memory 146036 kb
Host smart-dc7d3e51-fcfe-4a15-865b-db7e934f23f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777356994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1777356994
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.716338429
Short name T10
Test name
Test status
Simulation time 5031490 ps
CPU time 0.38 seconds
Started Jun 23 04:30:33 PM PDT 24
Finished Jun 23 04:30:34 PM PDT 24
Peak memory 146000 kb
Host smart-f95cbf4c-0346-458e-98b9-8c4dea2b5021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716338429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.716338429
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.544048975
Short name T5
Test name
Test status
Simulation time 4928854 ps
CPU time 0.37 seconds
Started Jun 23 04:30:53 PM PDT 24
Finished Jun 23 04:30:54 PM PDT 24
Peak memory 146000 kb
Host smart-a2aadf74-7cc5-4745-befa-155b72851744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544048975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.544048975
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1648230323
Short name T1
Test name
Test status
Simulation time 5153525 ps
CPU time 0.4 seconds
Started Jun 23 04:19:31 PM PDT 24
Finished Jun 23 04:19:32 PM PDT 24
Peak memory 145800 kb
Host smart-3b063402-7146-462b-a8b7-ba60722738bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648230323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1648230323
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.1490820123
Short name T12
Test name
Test status
Simulation time 4808623 ps
CPU time 0.38 seconds
Started Jun 23 04:22:51 PM PDT 24
Finished Jun 23 04:22:52 PM PDT 24
Peak memory 145788 kb
Host smart-5f6d56bd-c177-421e-8bd9-38f1452a38f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490820123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1490820123
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.188983410
Short name T7
Test name
Test status
Simulation time 4823478 ps
CPU time 0.42 seconds
Started Jun 23 04:23:15 PM PDT 24
Finished Jun 23 04:23:16 PM PDT 24
Peak memory 146364 kb
Host smart-0fca2562-4c4d-409c-af58-594b2bc7202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188983410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.188983410
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1972991566
Short name T15
Test name
Test status
Simulation time 4327295 ps
CPU time 0.36 seconds
Started Jun 23 04:21:28 PM PDT 24
Finished Jun 23 04:21:29 PM PDT 24
Peak memory 145788 kb
Host smart-fd6b4ee4-8b2a-49b6-9de9-0390c1613d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972991566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1972991566
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.969757271
Short name T19
Test name
Test status
Simulation time 5102029 ps
CPU time 0.4 seconds
Started Jun 23 04:20:12 PM PDT 24
Finished Jun 23 04:20:13 PM PDT 24
Peak memory 145828 kb
Host smart-d21c3e71-21ec-4730-83f0-11e8bbff597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969757271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.969757271
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.1392456518
Short name T17
Test name
Test status
Simulation time 5115057 ps
CPU time 0.39 seconds
Started Jun 23 04:19:56 PM PDT 24
Finished Jun 23 04:19:57 PM PDT 24
Peak memory 145640 kb
Host smart-5135d473-41b6-466e-b7ab-507142f6e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392456518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1392456518
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3155034988
Short name T18
Test name
Test status
Simulation time 5145544 ps
CPU time 0.4 seconds
Started Jun 23 04:19:42 PM PDT 24
Finished Jun 23 04:19:43 PM PDT 24
Peak memory 145604 kb
Host smart-f33e5a18-8a7a-4bef-ab3e-a8970f834e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155034988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3155034988
Directory /workspace/9.prim_esc_test/latest
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