| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.94 | 85.94 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/5.prim_esc_test.1994513066 |
| 87.67 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2317104256 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.3186933259 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.2522639500 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3802545541 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.864749854 |
| /workspace/coverage/default/11.prim_esc_test.3253547384 |
| /workspace/coverage/default/12.prim_esc_test.4042973846 |
| /workspace/coverage/default/13.prim_esc_test.856974139 |
| /workspace/coverage/default/14.prim_esc_test.3202335434 |
| /workspace/coverage/default/17.prim_esc_test.220470224 |
| /workspace/coverage/default/18.prim_esc_test.2916493265 |
| /workspace/coverage/default/19.prim_esc_test.3510266490 |
| /workspace/coverage/default/2.prim_esc_test.306833169 |
| /workspace/coverage/default/3.prim_esc_test.2966528187 |
| /workspace/coverage/default/4.prim_esc_test.3022550781 |
| /workspace/coverage/default/6.prim_esc_test.2575419607 |
| /workspace/coverage/default/7.prim_esc_test.593082912 |
| /workspace/coverage/default/8.prim_esc_test.4026246530 |
| /workspace/coverage/default/9.prim_esc_test.1332541201 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_esc_test.3510266490 | Jun 24 04:18:48 PM PDT 24 | Jun 24 04:18:49 PM PDT 24 | 5017181 ps | ||
| T2 | /workspace/coverage/default/17.prim_esc_test.220470224 | Jun 24 04:16:28 PM PDT 24 | Jun 24 04:16:29 PM PDT 24 | 5489391 ps | ||
| T3 | /workspace/coverage/default/8.prim_esc_test.4026246530 | Jun 24 04:16:27 PM PDT 24 | Jun 24 04:16:28 PM PDT 24 | 4932119 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.3202335434 | Jun 24 04:16:31 PM PDT 24 | Jun 24 04:16:32 PM PDT 24 | 4573532 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.2916493265 | Jun 24 04:16:18 PM PDT 24 | Jun 24 04:16:19 PM PDT 24 | 4833253 ps | ||
| T4 | /workspace/coverage/default/16.prim_esc_test.3186933259 | Jun 24 04:22:10 PM PDT 24 | Jun 24 04:22:11 PM PDT 24 | 4646848 ps | ||
| T6 | /workspace/coverage/default/12.prim_esc_test.4042973846 | Jun 24 04:17:55 PM PDT 24 | Jun 24 04:17:55 PM PDT 24 | 5043420 ps | ||
| T9 | /workspace/coverage/default/5.prim_esc_test.1994513066 | Jun 24 04:16:27 PM PDT 24 | Jun 24 04:16:28 PM PDT 24 | 4753531 ps | ||
| T10 | /workspace/coverage/default/9.prim_esc_test.1332541201 | Jun 24 04:21:47 PM PDT 24 | Jun 24 04:21:48 PM PDT 24 | 4486814 ps | ||
| T7 | /workspace/coverage/default/1.prim_esc_test.2522639500 | Jun 24 04:16:24 PM PDT 24 | Jun 24 04:16:25 PM PDT 24 | 4968928 ps | ||
| T13 | /workspace/coverage/default/15.prim_esc_test.3802545541 | Jun 24 04:16:21 PM PDT 24 | Jun 24 04:16:22 PM PDT 24 | 5116679 ps | ||
| T14 | /workspace/coverage/default/7.prim_esc_test.593082912 | Jun 24 04:16:48 PM PDT 24 | Jun 24 04:16:48 PM PDT 24 | 4742407 ps | ||
| T15 | /workspace/coverage/default/3.prim_esc_test.2966528187 | Jun 24 04:22:02 PM PDT 24 | Jun 24 04:22:03 PM PDT 24 | 4784367 ps | ||
| T11 | /workspace/coverage/default/11.prim_esc_test.3253547384 | Jun 24 04:16:22 PM PDT 24 | Jun 24 04:16:22 PM PDT 24 | 4943837 ps | ||
| T12 | /workspace/coverage/default/10.prim_esc_test.2317104256 | Jun 24 04:21:09 PM PDT 24 | Jun 24 04:21:10 PM PDT 24 | 4456429 ps | ||
| T17 | /workspace/coverage/default/13.prim_esc_test.856974139 | Jun 24 04:16:26 PM PDT 24 | Jun 24 04:16:27 PM PDT 24 | 4711831 ps | ||
| T18 | /workspace/coverage/default/4.prim_esc_test.3022550781 | Jun 24 04:16:22 PM PDT 24 | Jun 24 04:16:23 PM PDT 24 | 4916609 ps | ||
| T16 | /workspace/coverage/default/0.prim_esc_test.864749854 | Jun 24 04:18:48 PM PDT 24 | Jun 24 04:18:49 PM PDT 24 | 5212673 ps | ||
| T19 | /workspace/coverage/default/6.prim_esc_test.2575419607 | Jun 24 04:16:24 PM PDT 24 | Jun 24 04:16:25 PM PDT 24 | 4474398 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.306833169 | Jun 24 04:16:41 PM PDT 24 | Jun 24 04:16:42 PM PDT 24 | 4744802 ps |
| Test location | /workspace/coverage/default/5.prim_esc_test.1994513066 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4753531 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:27 PM PDT 24 |
| Finished | Jun 24 04:16:28 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-d2611472-0419-4ab9-8ff7-38d89860cbb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994513066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1994513066 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2317104256 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4456429 ps |
| CPU time | 0.41 seconds |
| Started | Jun 24 04:21:09 PM PDT 24 |
| Finished | Jun 24 04:21:10 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-9bc73d34-8c09-4d4d-acad-1944d447d4fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317104256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2317104256 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3186933259 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4646848 ps |
| CPU time | 0.42 seconds |
| Started | Jun 24 04:22:10 PM PDT 24 |
| Finished | Jun 24 04:22:11 PM PDT 24 |
| Peak memory | 146372 kb |
| Host | smart-4eb2fdb1-b19e-45c9-a55b-f19dcf9aa602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186933259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3186933259 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2522639500 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4968928 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:24 PM PDT 24 |
| Finished | Jun 24 04:16:25 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-6f18d70b-64fc-4dab-ae64-0c96a1472e04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522639500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2522639500 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3802545541 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5116679 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:21 PM PDT 24 |
| Finished | Jun 24 04:16:22 PM PDT 24 |
| Peak memory | 146784 kb |
| Host | smart-796bf204-43fb-48d0-bcb8-79da48d13fa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802545541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3802545541 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.864749854 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5212673 ps |
| CPU time | 0.39 seconds |
| Started | Jun 24 04:18:48 PM PDT 24 |
| Finished | Jun 24 04:18:49 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-7bdf7c7f-6159-425b-b6ac-2197aaa4ec7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864749854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.864749854 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3253547384 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4943837 ps |
| CPU time | 0.39 seconds |
| Started | Jun 24 04:16:22 PM PDT 24 |
| Finished | Jun 24 04:16:22 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-af8e2ca1-88d2-42bf-a812-76edb12fac83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253547384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3253547384 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.4042973846 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5043420 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:17:55 PM PDT 24 |
| Finished | Jun 24 04:17:55 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-0ec59071-286b-4c45-bf8c-768370b19ce8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042973846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4042973846 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.856974139 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4711831 ps |
| CPU time | 0.37 seconds |
| Started | Jun 24 04:16:26 PM PDT 24 |
| Finished | Jun 24 04:16:27 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-4133aae3-ad21-4265-9031-83d80fa8a684 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856974139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.856974139 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3202335434 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4573532 ps |
| CPU time | 0.4 seconds |
| Started | Jun 24 04:16:31 PM PDT 24 |
| Finished | Jun 24 04:16:32 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-d720cb63-43a3-4bc7-9fdf-ccd4d3dfc36d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202335434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3202335434 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.220470224 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5489391 ps |
| CPU time | 0.41 seconds |
| Started | Jun 24 04:16:28 PM PDT 24 |
| Finished | Jun 24 04:16:29 PM PDT 24 |
| Peak memory | 146288 kb |
| Host | smart-73cd9a3c-f479-4868-b0b4-d796330f5332 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220470224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.220470224 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2916493265 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4833253 ps |
| CPU time | 0.44 seconds |
| Started | Jun 24 04:16:18 PM PDT 24 |
| Finished | Jun 24 04:16:19 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-bf8dbda5-4ab9-4942-aa4b-268e0bf05f49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916493265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2916493265 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3510266490 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5017181 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:18:48 PM PDT 24 |
| Finished | Jun 24 04:18:49 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-d0b086df-7eb2-4104-bcb6-47fb14668ce0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510266490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3510266490 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.306833169 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4744802 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:41 PM PDT 24 |
| Finished | Jun 24 04:16:42 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-0384b927-f73f-4ed6-bd8d-649f29a1455b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306833169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.306833169 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2966528187 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4784367 ps |
| CPU time | 0.37 seconds |
| Started | Jun 24 04:22:02 PM PDT 24 |
| Finished | Jun 24 04:22:03 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-2daaa2e9-c0e1-43e0-97f2-2bdbf278f3b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966528187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2966528187 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3022550781 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4916609 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:22 PM PDT 24 |
| Finished | Jun 24 04:16:23 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-7243e8a2-a917-4c47-9c38-2c0ef388e7ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022550781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3022550781 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2575419607 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4474398 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:24 PM PDT 24 |
| Finished | Jun 24 04:16:25 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-b966166c-5630-4f83-8757-0a69bfe655d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575419607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2575419607 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.593082912 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4742407 ps |
| CPU time | 0.43 seconds |
| Started | Jun 24 04:16:48 PM PDT 24 |
| Finished | Jun 24 04:16:48 PM PDT 24 |
| Peak memory | 146316 kb |
| Host | smart-84f93b4e-1a9a-4f87-aff7-accbc92e9ac9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593082912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.593082912 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.4026246530 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4932119 ps |
| CPU time | 0.38 seconds |
| Started | Jun 24 04:16:27 PM PDT 24 |
| Finished | Jun 24 04:16:28 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-aca41a2e-9f33-432a-8237-fa71de7dc903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026246530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.4026246530 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1332541201 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4486814 ps |
| CPU time | 0.41 seconds |
| Started | Jun 24 04:21:47 PM PDT 24 |
| Finished | Jun 24 04:21:48 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-0adfa832-b62d-4cfb-9883-777b643a2e83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332541201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1332541201 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |