| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/13.prim_esc_test.1336926285 |
| 88.27 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.3787382556 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.3583146710 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1279619203 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.3377020363 |
| /workspace/coverage/default/11.prim_esc_test.1596389080 |
| /workspace/coverage/default/12.prim_esc_test.3449644687 |
| /workspace/coverage/default/15.prim_esc_test.3123707109 |
| /workspace/coverage/default/16.prim_esc_test.3315941740 |
| /workspace/coverage/default/17.prim_esc_test.3594961145 |
| /workspace/coverage/default/18.prim_esc_test.2006693081 |
| /workspace/coverage/default/19.prim_esc_test.2584480915 |
| /workspace/coverage/default/2.prim_esc_test.3140526547 |
| /workspace/coverage/default/3.prim_esc_test.2034963480 |
| /workspace/coverage/default/4.prim_esc_test.2484748063 |
| /workspace/coverage/default/5.prim_esc_test.1678179077 |
| /workspace/coverage/default/6.prim_esc_test.3699459319 |
| /workspace/coverage/default/7.prim_esc_test.703173350 |
| /workspace/coverage/default/8.prim_esc_test.496962074 |
| /workspace/coverage/default/9.prim_esc_test.651929949 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_esc_test.496962074 | Jun 26 04:18:40 PM PDT 24 | Jun 26 04:18:42 PM PDT 24 | 4641860 ps | ||
| T2 | /workspace/coverage/default/15.prim_esc_test.3123707109 | Jun 26 04:23:59 PM PDT 24 | Jun 26 04:24:00 PM PDT 24 | 5192906 ps | ||
| T3 | /workspace/coverage/default/6.prim_esc_test.3699459319 | Jun 26 04:20:05 PM PDT 24 | Jun 26 04:20:06 PM PDT 24 | 4984373 ps | ||
| T4 | /workspace/coverage/default/13.prim_esc_test.1336926285 | Jun 26 04:19:04 PM PDT 24 | Jun 26 04:19:06 PM PDT 24 | 4659183 ps | ||
| T10 | /workspace/coverage/default/3.prim_esc_test.2034963480 | Jun 26 04:23:33 PM PDT 24 | Jun 26 04:23:35 PM PDT 24 | 5035666 ps | ||
| T9 | /workspace/coverage/default/16.prim_esc_test.3315941740 | Jun 26 04:23:43 PM PDT 24 | Jun 26 04:23:45 PM PDT 24 | 4925963 ps | ||
| T7 | /workspace/coverage/default/12.prim_esc_test.3449644687 | Jun 26 04:23:35 PM PDT 24 | Jun 26 04:23:36 PM PDT 24 | 4933245 ps | ||
| T8 | /workspace/coverage/default/0.prim_esc_test.3787382556 | Jun 26 04:19:42 PM PDT 24 | Jun 26 04:19:43 PM PDT 24 | 4301962 ps | ||
| T5 | /workspace/coverage/default/1.prim_esc_test.3377020363 | Jun 26 04:19:01 PM PDT 24 | Jun 26 04:19:02 PM PDT 24 | 5065343 ps | ||
| T13 | /workspace/coverage/default/18.prim_esc_test.2006693081 | Jun 26 04:23:58 PM PDT 24 | Jun 26 04:23:59 PM PDT 24 | 5039430 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.3140526547 | Jun 26 04:19:44 PM PDT 24 | Jun 26 04:19:45 PM PDT 24 | 4495895 ps | ||
| T14 | /workspace/coverage/default/7.prim_esc_test.703173350 | Jun 26 04:18:40 PM PDT 24 | Jun 26 04:18:42 PM PDT 24 | 5521750 ps | ||
| T12 | /workspace/coverage/default/5.prim_esc_test.1678179077 | Jun 26 04:19:21 PM PDT 24 | Jun 26 04:19:22 PM PDT 24 | 5639542 ps | ||
| T15 | /workspace/coverage/default/17.prim_esc_test.3594961145 | Jun 26 04:24:06 PM PDT 24 | Jun 26 04:24:08 PM PDT 24 | 4931714 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.2484748063 | Jun 26 04:23:33 PM PDT 24 | Jun 26 04:23:35 PM PDT 24 | 5022396 ps | ||
| T16 | /workspace/coverage/default/19.prim_esc_test.2584480915 | Jun 26 04:22:48 PM PDT 24 | Jun 26 04:22:50 PM PDT 24 | 5101293 ps | ||
| T17 | /workspace/coverage/default/11.prim_esc_test.1596389080 | Jun 26 04:23:35 PM PDT 24 | Jun 26 04:23:37 PM PDT 24 | 5252463 ps | ||
| T18 | /workspace/coverage/default/10.prim_esc_test.1279619203 | Jun 26 04:23:59 PM PDT 24 | Jun 26 04:24:01 PM PDT 24 | 5497428 ps | ||
| T19 | /workspace/coverage/default/9.prim_esc_test.651929949 | Jun 26 04:18:59 PM PDT 24 | Jun 26 04:19:00 PM PDT 24 | 4374700 ps | ||
| T20 | /workspace/coverage/default/14.prim_esc_test.3583146710 | Jun 26 04:23:35 PM PDT 24 | Jun 26 04:23:37 PM PDT 24 | 5313844 ps |
| Test location | /workspace/coverage/default/13.prim_esc_test.1336926285 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4659183 ps |
| CPU time | 0.41 seconds |
| Started | Jun 26 04:19:04 PM PDT 24 |
| Finished | Jun 26 04:19:06 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-61dc5863-6820-4458-ac16-dd1b13640a1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336926285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1336926285 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3787382556 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4301962 ps |
| CPU time | 0.4 seconds |
| Started | Jun 26 04:19:42 PM PDT 24 |
| Finished | Jun 26 04:19:43 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-4f2051e2-e7f7-420f-be57-aecc9cce4288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787382556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3787382556 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3583146710 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5313844 ps |
| CPU time | 0.38 seconds |
| Started | Jun 26 04:23:35 PM PDT 24 |
| Finished | Jun 26 04:23:37 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-23a9f0cd-99dc-40f7-9368-5df2eb7e3638 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583146710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3583146710 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1279619203 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5497428 ps |
| CPU time | 0.37 seconds |
| Started | Jun 26 04:23:59 PM PDT 24 |
| Finished | Jun 26 04:24:01 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-effdf9dd-b0e5-4abf-a9fe-042e587d2013 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279619203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1279619203 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3377020363 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5065343 ps |
| CPU time | 0.44 seconds |
| Started | Jun 26 04:19:01 PM PDT 24 |
| Finished | Jun 26 04:19:02 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-60ca9392-9887-45ad-9371-f7235249ffc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377020363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3377020363 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1596389080 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5252463 ps |
| CPU time | 0.37 seconds |
| Started | Jun 26 04:23:35 PM PDT 24 |
| Finished | Jun 26 04:23:37 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-f02b1f10-3099-42d8-8b73-b0df05e184d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596389080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1596389080 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3449644687 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4933245 ps |
| CPU time | 0.37 seconds |
| Started | Jun 26 04:23:35 PM PDT 24 |
| Finished | Jun 26 04:23:36 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-8c991f10-3e24-4b11-a77e-092d5c83f216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449644687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3449644687 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3123707109 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5192906 ps |
| CPU time | 0.38 seconds |
| Started | Jun 26 04:23:59 PM PDT 24 |
| Finished | Jun 26 04:24:00 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-eabb6c5d-1394-499f-bba1-5fadda86975d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123707109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3123707109 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3315941740 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4925963 ps |
| CPU time | 0.39 seconds |
| Started | Jun 26 04:23:43 PM PDT 24 |
| Finished | Jun 26 04:23:45 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-d5efb6a6-4fb6-4af5-8ace-1c5bc342619f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315941740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3315941740 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3594961145 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4931714 ps |
| CPU time | 0.37 seconds |
| Started | Jun 26 04:24:06 PM PDT 24 |
| Finished | Jun 26 04:24:08 PM PDT 24 |
| Peak memory | 146796 kb |
| Host | smart-fc53eb81-4bfa-4955-aac2-0cb9592123bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594961145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3594961145 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2006693081 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5039430 ps |
| CPU time | 0.36 seconds |
| Started | Jun 26 04:23:58 PM PDT 24 |
| Finished | Jun 26 04:23:59 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-2c350512-eaba-49da-990f-13f44972e69f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006693081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2006693081 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2584480915 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5101293 ps |
| CPU time | 0.42 seconds |
| Started | Jun 26 04:22:48 PM PDT 24 |
| Finished | Jun 26 04:22:50 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-483f56d5-c946-48b4-8ca8-d5b2a805fb66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584480915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2584480915 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3140526547 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4495895 ps |
| CPU time | 0.45 seconds |
| Started | Jun 26 04:19:44 PM PDT 24 |
| Finished | Jun 26 04:19:45 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-3b695112-9ebb-4e84-9ca7-16aef5106622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140526547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3140526547 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2034963480 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5035666 ps |
| CPU time | 0.38 seconds |
| Started | Jun 26 04:23:33 PM PDT 24 |
| Finished | Jun 26 04:23:35 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-34b244ed-1e69-439a-b6a6-214e386e1674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034963480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2034963480 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2484748063 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5022396 ps |
| CPU time | 0.37 seconds |
| Started | Jun 26 04:23:33 PM PDT 24 |
| Finished | Jun 26 04:23:35 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-203d0153-3b8c-4607-a3ba-044b4ade5706 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484748063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2484748063 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1678179077 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5639542 ps |
| CPU time | 0.38 seconds |
| Started | Jun 26 04:19:21 PM PDT 24 |
| Finished | Jun 26 04:19:22 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-01989383-d7af-4029-a2a5-b406b39bf171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678179077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1678179077 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3699459319 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4984373 ps |
| CPU time | 0.38 seconds |
| Started | Jun 26 04:20:05 PM PDT 24 |
| Finished | Jun 26 04:20:06 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-27607a43-a119-484b-94d5-9d97bae7d590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699459319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3699459319 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.703173350 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5521750 ps |
| CPU time | 0.46 seconds |
| Started | Jun 26 04:18:40 PM PDT 24 |
| Finished | Jun 26 04:18:42 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-16539da0-1047-40ba-8298-6f157060feff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703173350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.703173350 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.496962074 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4641860 ps |
| CPU time | 0.44 seconds |
| Started | Jun 26 04:18:40 PM PDT 24 |
| Finished | Jun 26 04:18:42 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-e0de9cf1-24aa-4d1b-9970-28f881607fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496962074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.496962074 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.651929949 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4374700 ps |
| CPU time | 0.41 seconds |
| Started | Jun 26 04:18:59 PM PDT 24 |
| Finished | Jun 26 04:19:00 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-5e8dcdb0-c2c8-4203-8154-08c046be73e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651929949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.651929949 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |