Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.23 85.23 90.48 90.48 85.37 85.37 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/0.prim_esc_test.373962865
88.27 3.04 93.33 2.86 85.37 0.00 100.00 0.00 85.71 10.71 83.72 4.65 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.3661393766
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/4.prim_esc_test.775928263
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/17.prim_esc_test.182040472

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.3555244869
/workspace/coverage/default/10.prim_esc_test.1166872489
/workspace/coverage/default/11.prim_esc_test.1994392727
/workspace/coverage/default/12.prim_esc_test.203029365
/workspace/coverage/default/13.prim_esc_test.473835251
/workspace/coverage/default/14.prim_esc_test.1207972197
/workspace/coverage/default/15.prim_esc_test.1989222707
/workspace/coverage/default/16.prim_esc_test.2240993897
/workspace/coverage/default/18.prim_esc_test.2559279943
/workspace/coverage/default/2.prim_esc_test.3074228499
/workspace/coverage/default/3.prim_esc_test.1928024154
/workspace/coverage/default/5.prim_esc_test.1381423745
/workspace/coverage/default/6.prim_esc_test.2502166407
/workspace/coverage/default/7.prim_esc_test.4248925650
/workspace/coverage/default/8.prim_esc_test.1454223379
/workspace/coverage/default/9.prim_esc_test.489725364



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.prim_esc_test.1454223379 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:37 PM PDT 24 4867567 ps
T2 /workspace/coverage/default/9.prim_esc_test.489725364 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:38 PM PDT 24 5490827 ps
T3 /workspace/coverage/default/5.prim_esc_test.1381423745 Jun 27 04:17:43 PM PDT 24 Jun 27 04:17:45 PM PDT 24 5059967 ps
T4 /workspace/coverage/default/11.prim_esc_test.1994392727 Jun 27 04:22:40 PM PDT 24 Jun 27 04:22:42 PM PDT 24 5058372 ps
T5 /workspace/coverage/default/15.prim_esc_test.1989222707 Jun 27 04:18:41 PM PDT 24 Jun 27 04:18:42 PM PDT 24 4985802 ps
T6 /workspace/coverage/default/10.prim_esc_test.1166872489 Jun 27 04:23:19 PM PDT 24 Jun 27 04:23:29 PM PDT 24 4627452 ps
T15 /workspace/coverage/default/1.prim_esc_test.3555244869 Jun 27 04:23:30 PM PDT 24 Jun 27 04:23:44 PM PDT 24 4550888 ps
T9 /workspace/coverage/default/14.prim_esc_test.1207972197 Jun 27 04:18:25 PM PDT 24 Jun 27 04:18:27 PM PDT 24 5320314 ps
T12 /workspace/coverage/default/0.prim_esc_test.373962865 Jun 27 04:20:49 PM PDT 24 Jun 27 04:20:51 PM PDT 24 4313873 ps
T13 /workspace/coverage/default/16.prim_esc_test.2240993897 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:32 PM PDT 24 4805541 ps
T16 /workspace/coverage/default/7.prim_esc_test.4248925650 Jun 27 04:21:13 PM PDT 24 Jun 27 04:21:14 PM PDT 24 4865749 ps
T17 /workspace/coverage/default/18.prim_esc_test.2559279943 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 4921285 ps
T11 /workspace/coverage/default/12.prim_esc_test.203029365 Jun 27 04:19:18 PM PDT 24 Jun 27 04:19:20 PM PDT 24 4653850 ps
T18 /workspace/coverage/default/6.prim_esc_test.2502166407 Jun 27 04:17:26 PM PDT 24 Jun 27 04:17:28 PM PDT 24 4439882 ps
T10 /workspace/coverage/default/4.prim_esc_test.775928263 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:37 PM PDT 24 4246398 ps
T14 /workspace/coverage/default/17.prim_esc_test.182040472 Jun 27 04:23:08 PM PDT 24 Jun 27 04:23:12 PM PDT 24 4388064 ps
T19 /workspace/coverage/default/2.prim_esc_test.3074228499 Jun 27 04:23:18 PM PDT 24 Jun 27 04:23:29 PM PDT 24 4600196 ps
T7 /workspace/coverage/default/3.prim_esc_test.1928024154 Jun 27 04:23:19 PM PDT 24 Jun 27 04:23:29 PM PDT 24 4450569 ps
T8 /workspace/coverage/default/19.prim_esc_test.3661393766 Jun 27 04:22:25 PM PDT 24 Jun 27 04:22:27 PM PDT 24 4433964 ps
T20 /workspace/coverage/default/13.prim_esc_test.473835251 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:39 PM PDT 24 5190905 ps

Test location /workspace/coverage/default/0.prim_esc_test.373962865
Short name T12
Test name
Test status
Simulation time 4313873 ps
CPU time 0.42 seconds
Started Jun 27 04:20:49 PM PDT 24
Finished Jun 27 04:20:51 PM PDT 24
Peak memory 146328 kb
Host smart-4e1c8a96-a34a-4e2b-9511-06d99a298f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373962865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.373962865
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3661393766
Short name T8
Test name
Test status
Simulation time 4433964 ps
CPU time 0.42 seconds
Started Jun 27 04:22:25 PM PDT 24
Finished Jun 27 04:22:27 PM PDT 24
Peak memory 144388 kb
Host smart-3362d07b-ec56-4b2e-80b2-3fb36abd7f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661393766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3661393766
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.775928263
Short name T10
Test name
Test status
Simulation time 4246398 ps
CPU time 0.36 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:37 PM PDT 24
Peak memory 146052 kb
Host smart-c80cde07-df86-436e-b969-a2328cd7a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775928263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.775928263
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.182040472
Short name T14
Test name
Test status
Simulation time 4388064 ps
CPU time 0.36 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 145484 kb
Host smart-17b9ffb5-4ffe-435a-965d-1b8f9f6f4e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182040472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.182040472
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3555244869
Short name T15
Test name
Test status
Simulation time 4550888 ps
CPU time 0.37 seconds
Started Jun 27 04:23:30 PM PDT 24
Finished Jun 27 04:23:44 PM PDT 24
Peak memory 145876 kb
Host smart-87b22b6b-9cf6-4c7d-8c85-0453b1bee164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555244869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3555244869
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1166872489
Short name T6
Test name
Test status
Simulation time 4627452 ps
CPU time 0.37 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:29 PM PDT 24
Peak memory 145996 kb
Host smart-68f014f3-0307-41df-a120-2eb002af400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166872489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1166872489
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1994392727
Short name T4
Test name
Test status
Simulation time 5058372 ps
CPU time 0.36 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:42 PM PDT 24
Peak memory 145796 kb
Host smart-c9a7ad3a-efb0-47b0-9bb6-5234d10d8706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994392727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1994392727
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.203029365
Short name T11
Test name
Test status
Simulation time 4653850 ps
CPU time 0.39 seconds
Started Jun 27 04:19:18 PM PDT 24
Finished Jun 27 04:19:20 PM PDT 24
Peak memory 146020 kb
Host smart-31c44171-8072-4641-9f77-bda05a678b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203029365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.203029365
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.473835251
Short name T20
Test name
Test status
Simulation time 5190905 ps
CPU time 0.38 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:39 PM PDT 24
Peak memory 145780 kb
Host smart-5f2d6916-58c4-400b-99af-8ec77c75159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473835251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.473835251
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1207972197
Short name T9
Test name
Test status
Simulation time 5320314 ps
CPU time 0.37 seconds
Started Jun 27 04:18:25 PM PDT 24
Finished Jun 27 04:18:27 PM PDT 24
Peak memory 146012 kb
Host smart-a671796d-ecd8-48a0-a8c4-23ad842f6fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207972197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1207972197
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1989222707
Short name T5
Test name
Test status
Simulation time 4985802 ps
CPU time 0.36 seconds
Started Jun 27 04:18:41 PM PDT 24
Finished Jun 27 04:18:42 PM PDT 24
Peak memory 146016 kb
Host smart-2c7efb17-7fd5-4291-9f5e-ebed9699be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989222707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1989222707
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.2240993897
Short name T13
Test name
Test status
Simulation time 4805541 ps
CPU time 0.36 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 145960 kb
Host smart-bebca470-b3af-4ea4-95eb-b788d5f3c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240993897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2240993897
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2559279943
Short name T17
Test name
Test status
Simulation time 4921285 ps
CPU time 0.43 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 144924 kb
Host smart-f1ec250f-0be3-4f19-b13c-4d452db170f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559279943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2559279943
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3074228499
Short name T19
Test name
Test status
Simulation time 4600196 ps
CPU time 0.38 seconds
Started Jun 27 04:23:18 PM PDT 24
Finished Jun 27 04:23:29 PM PDT 24
Peak memory 145932 kb
Host smart-91be50aa-5407-4843-8b3c-4bcfaed775c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074228499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3074228499
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.1928024154
Short name T7
Test name
Test status
Simulation time 4450569 ps
CPU time 0.36 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:29 PM PDT 24
Peak memory 145932 kb
Host smart-3cc6fc2c-321f-441c-8e9d-67bd92864a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928024154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1928024154
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1381423745
Short name T3
Test name
Test status
Simulation time 5059967 ps
CPU time 0.42 seconds
Started Jun 27 04:17:43 PM PDT 24
Finished Jun 27 04:17:45 PM PDT 24
Peak memory 145944 kb
Host smart-f1edef96-475b-46a3-9134-ecaf69c36212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381423745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1381423745
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2502166407
Short name T18
Test name
Test status
Simulation time 4439882 ps
CPU time 0.48 seconds
Started Jun 27 04:17:26 PM PDT 24
Finished Jun 27 04:17:28 PM PDT 24
Peak memory 145468 kb
Host smart-befe43a0-0f65-4344-93c3-aab46b850ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502166407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2502166407
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.4248925650
Short name T16
Test name
Test status
Simulation time 4865749 ps
CPU time 0.39 seconds
Started Jun 27 04:21:13 PM PDT 24
Finished Jun 27 04:21:14 PM PDT 24
Peak memory 145956 kb
Host smart-a5ead7e6-d6e3-4f28-bc0b-039ab5f6861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248925650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4248925650
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.1454223379
Short name T1
Test name
Test status
Simulation time 4867567 ps
CPU time 0.37 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:37 PM PDT 24
Peak memory 146032 kb
Host smart-47d500e7-e68c-44a2-a894-005553b59552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454223379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1454223379
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.489725364
Short name T2
Test name
Test status
Simulation time 5490827 ps
CPU time 0.39 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:38 PM PDT 24
Peak memory 146056 kb
Host smart-d3b864db-d9e9-4e1e-a644-c406ed7a330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489725364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.489725364
Directory /workspace/9.prim_esc_test/latest
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