| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.01 | 94.29 | 85.37 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.83 | 84.83 | 90.48 | 90.48 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.2036798088 |
| 87.27 | 2.44 | 93.33 | 2.86 | 82.93 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.3671013310 |
| 88.82 | 1.55 | 94.29 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.3795383145 |
| 89.41 | 0.60 | 94.29 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.581794164 |
| 90.01 | 0.60 | 94.29 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.1271245539 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.2479756403 |
| /workspace/coverage/default/11.prim_esc_test.1967696837 |
| /workspace/coverage/default/12.prim_esc_test.345036763 |
| /workspace/coverage/default/13.prim_esc_test.1383710514 |
| /workspace/coverage/default/14.prim_esc_test.4280270187 |
| /workspace/coverage/default/16.prim_esc_test.946828121 |
| /workspace/coverage/default/18.prim_esc_test.3023659348 |
| /workspace/coverage/default/19.prim_esc_test.3667373477 |
| /workspace/coverage/default/2.prim_esc_test.219550475 |
| /workspace/coverage/default/3.prim_esc_test.3939039676 |
| /workspace/coverage/default/5.prim_esc_test.3542284694 |
| /workspace/coverage/default/6.prim_esc_test.2714343192 |
| /workspace/coverage/default/7.prim_esc_test.367786881 |
| /workspace/coverage/default/8.prim_esc_test.1223544303 |
| /workspace/coverage/default/9.prim_esc_test.2623450193 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_esc_test.946828121 | Jun 28 04:20:40 PM PDT 24 | Jun 28 04:20:41 PM PDT 24 | 4687232 ps | ||
| T2 | /workspace/coverage/default/9.prim_esc_test.2623450193 | Jun 28 04:23:04 PM PDT 24 | Jun 28 04:23:05 PM PDT 24 | 4817847 ps | ||
| T3 | /workspace/coverage/default/4.prim_esc_test.3795383145 | Jun 28 04:22:46 PM PDT 24 | Jun 28 04:22:47 PM PDT 24 | 5324382 ps | ||
| T13 | /workspace/coverage/default/15.prim_esc_test.581794164 | Jun 28 04:18:43 PM PDT 24 | Jun 28 04:18:44 PM PDT 24 | 4606109 ps | ||
| T4 | /workspace/coverage/default/7.prim_esc_test.367786881 | Jun 28 04:18:18 PM PDT 24 | Jun 28 04:18:19 PM PDT 24 | 4818632 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.1967696837 | Jun 28 04:19:48 PM PDT 24 | Jun 28 04:19:49 PM PDT 24 | 4571970 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.3939039676 | Jun 28 04:19:25 PM PDT 24 | Jun 28 04:19:26 PM PDT 24 | 4896781 ps | ||
| T5 | /workspace/coverage/default/8.prim_esc_test.1223544303 | Jun 28 04:18:17 PM PDT 24 | Jun 28 04:18:18 PM PDT 24 | 5412789 ps | ||
| T15 | /workspace/coverage/default/6.prim_esc_test.2714343192 | Jun 28 04:19:37 PM PDT 24 | Jun 28 04:19:37 PM PDT 24 | 4466750 ps | ||
| T9 | /workspace/coverage/default/1.prim_esc_test.2036798088 | Jun 28 04:22:47 PM PDT 24 | Jun 28 04:22:48 PM PDT 24 | 4901823 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.2479756403 | Jun 28 04:18:22 PM PDT 24 | Jun 28 04:18:23 PM PDT 24 | 5042454 ps | ||
| T16 | /workspace/coverage/default/13.prim_esc_test.1383710514 | Jun 28 04:22:28 PM PDT 24 | Jun 28 04:22:30 PM PDT 24 | 5241421 ps | ||
| T6 | /workspace/coverage/default/18.prim_esc_test.3023659348 | Jun 28 04:21:36 PM PDT 24 | Jun 28 04:21:37 PM PDT 24 | 4224207 ps | ||
| T17 | /workspace/coverage/default/12.prim_esc_test.345036763 | Jun 28 04:21:27 PM PDT 24 | Jun 28 04:21:28 PM PDT 24 | 5092507 ps | ||
| T18 | /workspace/coverage/default/2.prim_esc_test.219550475 | Jun 28 04:23:14 PM PDT 24 | Jun 28 04:23:15 PM PDT 24 | 5283916 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.3667373477 | Jun 28 04:20:59 PM PDT 24 | Jun 28 04:21:00 PM PDT 24 | 4779018 ps | ||
| T11 | /workspace/coverage/default/5.prim_esc_test.3542284694 | Jun 28 04:22:56 PM PDT 24 | Jun 28 04:22:56 PM PDT 24 | 4914807 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.1271245539 | Jun 28 04:22:28 PM PDT 24 | Jun 28 04:22:29 PM PDT 24 | 4840533 ps | ||
| T7 | /workspace/coverage/default/0.prim_esc_test.3671013310 | Jun 28 04:22:47 PM PDT 24 | Jun 28 04:22:48 PM PDT 24 | 4271290 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.4280270187 | Jun 28 04:18:19 PM PDT 24 | Jun 28 04:18:20 PM PDT 24 | 4686076 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.2036798088 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4901823 ps |
| CPU time | 0.38 seconds |
| Started | Jun 28 04:22:47 PM PDT 24 |
| Finished | Jun 28 04:22:48 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-695bfa0e-a2b4-4c81-b3f4-7a53661df604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036798088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2036798088 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3671013310 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4271290 ps |
| CPU time | 0.38 seconds |
| Started | Jun 28 04:22:47 PM PDT 24 |
| Finished | Jun 28 04:22:48 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-d7ff2212-ba47-444d-81bd-236495666867 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671013310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3671013310 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3795383145 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5324382 ps |
| CPU time | 0.38 seconds |
| Started | Jun 28 04:22:46 PM PDT 24 |
| Finished | Jun 28 04:22:47 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-5a43558f-6e16-4668-85ba-93da76b88b52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795383145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3795383145 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.581794164 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4606109 ps |
| CPU time | 0.39 seconds |
| Started | Jun 28 04:18:43 PM PDT 24 |
| Finished | Jun 28 04:18:44 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-8410ad0f-444d-49a1-af70-f38bd8ccefa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581794164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.581794164 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1271245539 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4840533 ps |
| CPU time | 0.42 seconds |
| Started | Jun 28 04:22:28 PM PDT 24 |
| Finished | Jun 28 04:22:29 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-312f7b17-91bd-40e9-a8cf-be3a68ca3e37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271245539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1271245539 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2479756403 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5042454 ps |
| CPU time | 0.41 seconds |
| Started | Jun 28 04:18:22 PM PDT 24 |
| Finished | Jun 28 04:18:23 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-24f3d17b-2872-4fbd-bba2-1371c654eff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479756403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2479756403 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1967696837 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4571970 ps |
| CPU time | 0.39 seconds |
| Started | Jun 28 04:19:48 PM PDT 24 |
| Finished | Jun 28 04:19:49 PM PDT 24 |
| Peak memory | 146100 kb |
| Host | smart-b9dabe23-4355-444e-82f2-0cdfacc759ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967696837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1967696837 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.345036763 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5092507 ps |
| CPU time | 0.38 seconds |
| Started | Jun 28 04:21:27 PM PDT 24 |
| Finished | Jun 28 04:21:28 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-5dd993c2-2cdd-4609-9f22-ba3cb98a519c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345036763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.345036763 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1383710514 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5241421 ps |
| CPU time | 0.37 seconds |
| Started | Jun 28 04:22:28 PM PDT 24 |
| Finished | Jun 28 04:22:30 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-cb555d95-a15c-4b55-a44b-6ac0e845caf0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383710514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1383710514 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.4280270187 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4686076 ps |
| CPU time | 0.42 seconds |
| Started | Jun 28 04:18:19 PM PDT 24 |
| Finished | Jun 28 04:18:20 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-cdfb028e-8e13-4ebc-b18b-9e1cb320cfd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280270187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4280270187 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.946828121 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4687232 ps |
| CPU time | 0.39 seconds |
| Started | Jun 28 04:20:40 PM PDT 24 |
| Finished | Jun 28 04:20:41 PM PDT 24 |
| Peak memory | 146264 kb |
| Host | smart-f66f6876-1d93-4d8d-920d-4b648d6929c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946828121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.946828121 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3023659348 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4224207 ps |
| CPU time | 0.38 seconds |
| Started | Jun 28 04:21:36 PM PDT 24 |
| Finished | Jun 28 04:21:37 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-9156286a-c051-4a95-9101-79db78d3ec7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023659348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3023659348 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3667373477 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4779018 ps |
| CPU time | 0.39 seconds |
| Started | Jun 28 04:20:59 PM PDT 24 |
| Finished | Jun 28 04:21:00 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-b4f9c262-bc8d-4adf-99b3-3acb9ea29761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667373477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3667373477 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.219550475 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5283916 ps |
| CPU time | 0.42 seconds |
| Started | Jun 28 04:23:14 PM PDT 24 |
| Finished | Jun 28 04:23:15 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-512013e6-ca4c-423f-8e93-363fb4fc0aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219550475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.219550475 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3939039676 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4896781 ps |
| CPU time | 0.4 seconds |
| Started | Jun 28 04:19:25 PM PDT 24 |
| Finished | Jun 28 04:19:26 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-308ec299-1339-47c7-b48f-f97b91e62791 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939039676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3939039676 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3542284694 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4914807 ps |
| CPU time | 0.38 seconds |
| Started | Jun 28 04:22:56 PM PDT 24 |
| Finished | Jun 28 04:22:56 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-5cbeef61-1749-4373-878d-f6cf2281469c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542284694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3542284694 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2714343192 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4466750 ps |
| CPU time | 0.37 seconds |
| Started | Jun 28 04:19:37 PM PDT 24 |
| Finished | Jun 28 04:19:37 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-f86ba080-7f87-4fe9-bb5a-a8553c5ded65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714343192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2714343192 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.367786881 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4818632 ps |
| CPU time | 0.4 seconds |
| Started | Jun 28 04:18:18 PM PDT 24 |
| Finished | Jun 28 04:18:19 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-42efa12c-aa83-4482-9af9-ea58605fc9d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367786881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.367786881 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1223544303 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5412789 ps |
| CPU time | 0.42 seconds |
| Started | Jun 28 04:18:17 PM PDT 24 |
| Finished | Jun 28 04:18:18 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-850b6405-fbaf-4ae1-8834-654af5f9b6ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223544303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1223544303 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2623450193 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4817847 ps |
| CPU time | 0.41 seconds |
| Started | Jun 28 04:23:04 PM PDT 24 |
| Finished | Jun 28 04:23:05 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-ec84aec2-002e-4f60-96bb-7723b50df309 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623450193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2623450193 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |