| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.64 | 84.64 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 71.43 | 71.43 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/0.prim_esc_test.239625502 |
| 87.67 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 82.14 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.4066728447 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.1113341004 |
| 91.15 | 1.74 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 7.14 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.1845658326 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.1475232945 |
| /workspace/coverage/default/12.prim_esc_test.2784121522 |
| /workspace/coverage/default/13.prim_esc_test.2862308096 |
| /workspace/coverage/default/14.prim_esc_test.226209937 |
| /workspace/coverage/default/15.prim_esc_test.355178373 |
| /workspace/coverage/default/16.prim_esc_test.223319705 |
| /workspace/coverage/default/17.prim_esc_test.1164208375 |
| /workspace/coverage/default/19.prim_esc_test.2638350545 |
| /workspace/coverage/default/2.prim_esc_test.3826020035 |
| /workspace/coverage/default/3.prim_esc_test.2737934270 |
| /workspace/coverage/default/4.prim_esc_test.2780175518 |
| /workspace/coverage/default/5.prim_esc_test.1412061608 |
| /workspace/coverage/default/6.prim_esc_test.1813029955 |
| /workspace/coverage/default/7.prim_esc_test.966016354 |
| /workspace/coverage/default/8.prim_esc_test.45947252 |
| /workspace/coverage/default/9.prim_esc_test.2786629901 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_esc_test.2786629901 | Jun 29 04:17:54 PM PDT 24 | Jun 29 04:17:56 PM PDT 24 | 4975583 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.1113341004 | Jun 29 04:22:34 PM PDT 24 | Jun 29 04:22:35 PM PDT 24 | 4864265 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.1475232945 | Jun 29 04:17:55 PM PDT 24 | Jun 29 04:17:57 PM PDT 24 | 5037208 ps | ||
| T5 | /workspace/coverage/default/2.prim_esc_test.3826020035 | Jun 29 04:17:48 PM PDT 24 | Jun 29 04:17:49 PM PDT 24 | 5102770 ps | ||
| T4 | /workspace/coverage/default/0.prim_esc_test.239625502 | Jun 29 04:19:08 PM PDT 24 | Jun 29 04:19:09 PM PDT 24 | 4628544 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.1164208375 | Jun 29 04:18:52 PM PDT 24 | Jun 29 04:18:54 PM PDT 24 | 4877616 ps | ||
| T9 | /workspace/coverage/default/8.prim_esc_test.45947252 | Jun 29 04:17:53 PM PDT 24 | Jun 29 04:17:55 PM PDT 24 | 4974686 ps | ||
| T11 | /workspace/coverage/default/14.prim_esc_test.226209937 | Jun 29 04:22:17 PM PDT 24 | Jun 29 04:22:17 PM PDT 24 | 4283472 ps | ||
| T7 | /workspace/coverage/default/13.prim_esc_test.2862308096 | Jun 29 04:18:45 PM PDT 24 | Jun 29 04:18:46 PM PDT 24 | 5199797 ps | ||
| T10 | /workspace/coverage/default/19.prim_esc_test.2638350545 | Jun 29 04:18:47 PM PDT 24 | Jun 29 04:18:47 PM PDT 24 | 5162427 ps | ||
| T15 | /workspace/coverage/default/3.prim_esc_test.2737934270 | Jun 29 04:22:34 PM PDT 24 | Jun 29 04:22:35 PM PDT 24 | 4896550 ps | ||
| T13 | /workspace/coverage/default/11.prim_esc_test.1845658326 | Jun 29 04:18:45 PM PDT 24 | Jun 29 04:18:46 PM PDT 24 | 4849812 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.355178373 | Jun 29 04:19:08 PM PDT 24 | Jun 29 04:19:08 PM PDT 24 | 5343542 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.223319705 | Jun 29 04:18:53 PM PDT 24 | Jun 29 04:18:54 PM PDT 24 | 5064075 ps | ||
| T17 | /workspace/coverage/default/4.prim_esc_test.2780175518 | Jun 29 04:22:50 PM PDT 24 | Jun 29 04:22:51 PM PDT 24 | 4927048 ps | ||
| T12 | /workspace/coverage/default/7.prim_esc_test.966016354 | Jun 29 04:21:54 PM PDT 24 | Jun 29 04:21:55 PM PDT 24 | 4629506 ps | ||
| T18 | /workspace/coverage/default/12.prim_esc_test.2784121522 | Jun 29 04:19:08 PM PDT 24 | Jun 29 04:19:09 PM PDT 24 | 4913229 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.4066728447 | Jun 29 04:18:52 PM PDT 24 | Jun 29 04:18:54 PM PDT 24 | 4823297 ps | ||
| T19 | /workspace/coverage/default/6.prim_esc_test.1813029955 | Jun 29 04:17:54 PM PDT 24 | Jun 29 04:17:56 PM PDT 24 | 4915335 ps | ||
| T20 | /workspace/coverage/default/5.prim_esc_test.1412061608 | Jun 29 04:17:54 PM PDT 24 | Jun 29 04:17:57 PM PDT 24 | 4781878 ps |
| Test location | /workspace/coverage/default/0.prim_esc_test.239625502 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4628544 ps |
| CPU time | 0.38 seconds |
| Started | Jun 29 04:19:08 PM PDT 24 |
| Finished | Jun 29 04:19:09 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-f13a7151-0258-425b-9314-a97733db36fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=239625502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.239625502 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.4066728447 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4823297 ps |
| CPU time | 0.42 seconds |
| Started | Jun 29 04:18:52 PM PDT 24 |
| Finished | Jun 29 04:18:54 PM PDT 24 |
| Peak memory | 144356 kb |
| Host | smart-f0f081ed-bf50-4920-bd94-cfd98bf04390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066728447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.4066728447 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1113341004 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4864265 ps |
| CPU time | 0.4 seconds |
| Started | Jun 29 04:22:34 PM PDT 24 |
| Finished | Jun 29 04:22:35 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-0e82a455-2a26-4c74-94ee-224e36e5cfc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113341004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1113341004 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1845658326 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4849812 ps |
| CPU time | 0.37 seconds |
| Started | Jun 29 04:18:45 PM PDT 24 |
| Finished | Jun 29 04:18:46 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-7b114896-6957-4d7a-903e-cb5112edb3b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845658326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1845658326 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1475232945 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5037208 ps |
| CPU time | 0.37 seconds |
| Started | Jun 29 04:17:55 PM PDT 24 |
| Finished | Jun 29 04:17:57 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-1d3a61ec-3437-46ce-a944-3e5547e50664 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475232945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1475232945 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2784121522 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4913229 ps |
| CPU time | 0.39 seconds |
| Started | Jun 29 04:19:08 PM PDT 24 |
| Finished | Jun 29 04:19:09 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-d7cc6fd0-0e8f-4048-b4be-644e75011049 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784121522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2784121522 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2862308096 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5199797 ps |
| CPU time | 0.38 seconds |
| Started | Jun 29 04:18:45 PM PDT 24 |
| Finished | Jun 29 04:18:46 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-f21a85fd-97ad-4996-82cb-ebe6340f9d6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862308096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2862308096 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.226209937 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4283472 ps |
| CPU time | 0.37 seconds |
| Started | Jun 29 04:22:17 PM PDT 24 |
| Finished | Jun 29 04:22:17 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-38e6781a-492c-41c6-9492-a999abee58f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226209937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.226209937 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.355178373 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5343542 ps |
| CPU time | 0.37 seconds |
| Started | Jun 29 04:19:08 PM PDT 24 |
| Finished | Jun 29 04:19:08 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-f9fcdafa-aa0c-46f8-83b9-e14c17f8748e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355178373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.355178373 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.223319705 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5064075 ps |
| CPU time | 0.42 seconds |
| Started | Jun 29 04:18:53 PM PDT 24 |
| Finished | Jun 29 04:18:54 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-b12cee71-0d28-4ea9-8b0b-2f58551660af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223319705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.223319705 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1164208375 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4877616 ps |
| CPU time | 0.41 seconds |
| Started | Jun 29 04:18:52 PM PDT 24 |
| Finished | Jun 29 04:18:54 PM PDT 24 |
| Peak memory | 144172 kb |
| Host | smart-63a74773-a46b-404f-a504-019c7fb3e035 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164208375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1164208375 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2638350545 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5162427 ps |
| CPU time | 0.42 seconds |
| Started | Jun 29 04:18:47 PM PDT 24 |
| Finished | Jun 29 04:18:47 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-704849ab-6c37-4002-acc2-dc8be50d9501 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638350545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2638350545 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3826020035 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5102770 ps |
| CPU time | 0.42 seconds |
| Started | Jun 29 04:17:48 PM PDT 24 |
| Finished | Jun 29 04:17:49 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-734293c7-46c6-431b-80e3-ca2022ea1171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826020035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3826020035 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2737934270 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4896550 ps |
| CPU time | 0.4 seconds |
| Started | Jun 29 04:22:34 PM PDT 24 |
| Finished | Jun 29 04:22:35 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-d6f3d892-3384-49fd-9af3-4f47b05ac4b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737934270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2737934270 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2780175518 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4927048 ps |
| CPU time | 0.38 seconds |
| Started | Jun 29 04:22:50 PM PDT 24 |
| Finished | Jun 29 04:22:51 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-338989c5-7f71-44af-b606-aaa3b95a7e9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780175518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2780175518 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1412061608 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4781878 ps |
| CPU time | 0.36 seconds |
| Started | Jun 29 04:17:54 PM PDT 24 |
| Finished | Jun 29 04:17:57 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-8ffc8467-f690-4aeb-ae7f-09f3ac620500 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412061608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1412061608 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1813029955 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4915335 ps |
| CPU time | 0.52 seconds |
| Started | Jun 29 04:17:54 PM PDT 24 |
| Finished | Jun 29 04:17:56 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-610f1e1e-2810-43b0-8c8f-0765936dea37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813029955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1813029955 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.966016354 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4629506 ps |
| CPU time | 0.39 seconds |
| Started | Jun 29 04:21:54 PM PDT 24 |
| Finished | Jun 29 04:21:55 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-de42a0ee-6336-4ca1-9cf3-0f3a1e43a23c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966016354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.966016354 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.45947252 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4974686 ps |
| CPU time | 0.4 seconds |
| Started | Jun 29 04:17:53 PM PDT 24 |
| Finished | Jun 29 04:17:55 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-7984f5f1-531d-4032-a8bc-244bd3e96a23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45947252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.45947252 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2786629901 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4975583 ps |
| CPU time | 0.38 seconds |
| Started | Jun 29 04:17:54 PM PDT 24 |
| Finished | Jun 29 04:17:56 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-09071e73-866f-4913-9fe0-712dfad3c325 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786629901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2786629901 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |