| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/10.prim_esc_test.3775384245 |
| 88.27 | 2.74 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.3143517136 |
| 89.41 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3728715929 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1975761148 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.349037193 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.4026632355 |
| /workspace/coverage/default/11.prim_esc_test.402886914 |
| /workspace/coverage/default/12.prim_esc_test.1631985106 |
| /workspace/coverage/default/15.prim_esc_test.3319977688 |
| /workspace/coverage/default/16.prim_esc_test.3733999960 |
| /workspace/coverage/default/17.prim_esc_test.3802050077 |
| /workspace/coverage/default/18.prim_esc_test.62268785 |
| /workspace/coverage/default/19.prim_esc_test.4275814687 |
| /workspace/coverage/default/2.prim_esc_test.2652199919 |
| /workspace/coverage/default/3.prim_esc_test.1020752664 |
| /workspace/coverage/default/4.prim_esc_test.3342030036 |
| /workspace/coverage/default/5.prim_esc_test.2174475593 |
| /workspace/coverage/default/6.prim_esc_test.1315554429 |
| /workspace/coverage/default/8.prim_esc_test.3807370552 |
| /workspace/coverage/default/9.prim_esc_test.308392269 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_esc_test.3775384245 | Jun 30 04:22:38 PM PDT 24 | Jun 30 04:22:40 PM PDT 24 | 4839839 ps | ||
| T2 | /workspace/coverage/default/12.prim_esc_test.1631985106 | Jun 30 04:17:33 PM PDT 24 | Jun 30 04:17:34 PM PDT 24 | 4403798 ps | ||
| T3 | /workspace/coverage/default/8.prim_esc_test.3807370552 | Jun 30 04:23:00 PM PDT 24 | Jun 30 04:23:02 PM PDT 24 | 4880859 ps | ||
| T4 | /workspace/coverage/default/1.prim_esc_test.4026632355 | Jun 30 04:23:00 PM PDT 24 | Jun 30 04:23:02 PM PDT 24 | 4901153 ps | ||
| T7 | /workspace/coverage/default/17.prim_esc_test.3802050077 | Jun 30 04:18:17 PM PDT 24 | Jun 30 04:18:18 PM PDT 24 | 4256555 ps | ||
| T5 | /workspace/coverage/default/7.prim_esc_test.3143517136 | Jun 30 04:17:19 PM PDT 24 | Jun 30 04:17:20 PM PDT 24 | 4663521 ps | ||
| T6 | /workspace/coverage/default/9.prim_esc_test.308392269 | Jun 30 04:22:37 PM PDT 24 | Jun 30 04:22:39 PM PDT 24 | 4721759 ps | ||
| T14 | /workspace/coverage/default/16.prim_esc_test.3733999960 | Jun 30 04:17:55 PM PDT 24 | Jun 30 04:17:56 PM PDT 24 | 4979481 ps | ||
| T8 | /workspace/coverage/default/5.prim_esc_test.2174475593 | Jun 30 04:22:59 PM PDT 24 | Jun 30 04:23:00 PM PDT 24 | 4856572 ps | ||
| T9 | /workspace/coverage/default/0.prim_esc_test.349037193 | Jun 30 04:22:40 PM PDT 24 | Jun 30 04:22:43 PM PDT 24 | 5517980 ps | ||
| T16 | /workspace/coverage/default/2.prim_esc_test.2652199919 | Jun 30 04:22:35 PM PDT 24 | Jun 30 04:22:37 PM PDT 24 | 4391836 ps | ||
| T10 | /workspace/coverage/default/14.prim_esc_test.1975761148 | Jun 30 04:17:39 PM PDT 24 | Jun 30 04:17:40 PM PDT 24 | 5121050 ps | ||
| T11 | /workspace/coverage/default/4.prim_esc_test.3342030036 | Jun 30 04:22:48 PM PDT 24 | Jun 30 04:22:51 PM PDT 24 | 4977588 ps | ||
| T12 | /workspace/coverage/default/6.prim_esc_test.1315554429 | Jun 30 04:17:14 PM PDT 24 | Jun 30 04:17:14 PM PDT 24 | 4797723 ps | ||
| T15 | /workspace/coverage/default/3.prim_esc_test.1020752664 | Jun 30 04:21:03 PM PDT 24 | Jun 30 04:21:03 PM PDT 24 | 5068935 ps | ||
| T13 | /workspace/coverage/default/13.prim_esc_test.3728715929 | Jun 30 04:18:45 PM PDT 24 | Jun 30 04:18:46 PM PDT 24 | 4467878 ps | ||
| T17 | /workspace/coverage/default/19.prim_esc_test.4275814687 | Jun 30 04:22:17 PM PDT 24 | Jun 30 04:22:18 PM PDT 24 | 5094379 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.62268785 | Jun 30 04:22:47 PM PDT 24 | Jun 30 04:22:50 PM PDT 24 | 5296649 ps | ||
| T19 | /workspace/coverage/default/11.prim_esc_test.402886914 | Jun 30 04:20:06 PM PDT 24 | Jun 30 04:20:07 PM PDT 24 | 5346616 ps | ||
| T20 | /workspace/coverage/default/15.prim_esc_test.3319977688 | Jun 30 04:17:53 PM PDT 24 | Jun 30 04:17:53 PM PDT 24 | 4882729 ps |
| Test location | /workspace/coverage/default/10.prim_esc_test.3775384245 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4839839 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:22:38 PM PDT 24 |
| Finished | Jun 30 04:22:40 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-909ad92d-f7fe-4113-b0d8-9a79ae64bbc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775384245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3775384245 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3143517136 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4663521 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:17:19 PM PDT 24 |
| Finished | Jun 30 04:17:20 PM PDT 24 |
| Peak memory | 145920 kb |
| Host | smart-31f902cc-383e-4ffb-9677-b1e7d40deffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143517136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3143517136 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3728715929 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4467878 ps |
| CPU time | 0.37 seconds |
| Started | Jun 30 04:18:45 PM PDT 24 |
| Finished | Jun 30 04:18:46 PM PDT 24 |
| Peak memory | 145988 kb |
| Host | smart-a42417e1-52ee-46f9-baa6-e93c4febf0ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728715929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3728715929 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1975761148 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5121050 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:17:39 PM PDT 24 |
| Finished | Jun 30 04:17:40 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-f62dc315-c7fa-4b7d-b598-b80fff7ae3ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975761148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1975761148 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.349037193 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5517980 ps |
| CPU time | 0.46 seconds |
| Started | Jun 30 04:22:40 PM PDT 24 |
| Finished | Jun 30 04:22:43 PM PDT 24 |
| Peak memory | 144320 kb |
| Host | smart-346ccc41-19cd-4409-a33c-8a1f2c7c6f44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349037193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.349037193 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4026632355 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4901153 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:23:00 PM PDT 24 |
| Finished | Jun 30 04:23:02 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-ced65f3c-6a1b-4644-a76d-68ab5f7d17b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026632355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4026632355 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.402886914 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5346616 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:20:06 PM PDT 24 |
| Finished | Jun 30 04:20:07 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-cbc1a3e6-a365-473d-b2d8-35a204b0474a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402886914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.402886914 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1631985106 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4403798 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:17:33 PM PDT 24 |
| Finished | Jun 30 04:17:34 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-170ab97d-2959-468b-b353-e910b831a9bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631985106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1631985106 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3319977688 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4882729 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:17:53 PM PDT 24 |
| Finished | Jun 30 04:17:53 PM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-f6816cc7-5d35-42c0-a181-b78566920112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319977688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3319977688 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3733999960 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4979481 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:17:55 PM PDT 24 |
| Finished | Jun 30 04:17:56 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-9396ef61-7b79-478e-881f-d887a1665962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733999960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3733999960 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3802050077 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4256555 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:18:17 PM PDT 24 |
| Finished | Jun 30 04:18:18 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-60749dbd-4ac8-435c-958b-0e6aef9aaa70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802050077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3802050077 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.62268785 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5296649 ps |
| CPU time | 0.37 seconds |
| Started | Jun 30 04:22:47 PM PDT 24 |
| Finished | Jun 30 04:22:50 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-ef321760-8e5f-431d-a378-26e463988df0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62268785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.62268785 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.4275814687 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5094379 ps |
| CPU time | 0.36 seconds |
| Started | Jun 30 04:22:17 PM PDT 24 |
| Finished | Jun 30 04:22:18 PM PDT 24 |
| Peak memory | 146812 kb |
| Host | smart-4ccfa94c-8cf7-4e2a-a3dd-28c639551668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275814687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4275814687 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2652199919 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4391836 ps |
| CPU time | 0.36 seconds |
| Started | Jun 30 04:22:35 PM PDT 24 |
| Finished | Jun 30 04:22:37 PM PDT 24 |
| Peak memory | 146652 kb |
| Host | smart-95f256de-615d-4ccf-9639-2a777012a82a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652199919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2652199919 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1020752664 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5068935 ps |
| CPU time | 0.43 seconds |
| Started | Jun 30 04:21:03 PM PDT 24 |
| Finished | Jun 30 04:21:03 PM PDT 24 |
| Peak memory | 145872 kb |
| Host | smart-3c6138d4-c3f3-46e6-b4bb-f6075f5ee1f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020752664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1020752664 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3342030036 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4977588 ps |
| CPU time | 0.36 seconds |
| Started | Jun 30 04:22:48 PM PDT 24 |
| Finished | Jun 30 04:22:51 PM PDT 24 |
| Peak memory | 146792 kb |
| Host | smart-c40fd5a4-b9b0-4c60-9c23-4425402e4d71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342030036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3342030036 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2174475593 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4856572 ps |
| CPU time | 0.37 seconds |
| Started | Jun 30 04:22:59 PM PDT 24 |
| Finished | Jun 30 04:23:00 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-bf716763-ac17-4aa7-b5e3-f4f64948d557 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174475593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2174475593 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1315554429 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4797723 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:17:14 PM PDT 24 |
| Finished | Jun 30 04:17:14 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-caa64342-1085-4b8e-b10b-bcf0c1bcb25d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315554429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1315554429 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3807370552 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4880859 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:23:00 PM PDT 24 |
| Finished | Jun 30 04:23:02 PM PDT 24 |
| Peak memory | 145920 kb |
| Host | smart-00fa2eca-3d90-427d-ab07-dbbfd3268996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807370552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3807370552 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.308392269 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4721759 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:22:37 PM PDT 24 |
| Finished | Jun 30 04:22:39 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-81151975-8200-4cf8-a171-8523ad6365c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308392269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.308392269 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |