| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.83 | 84.83 | 90.48 | 90.48 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/11.prim_esc_test.4000242025 |
| 88.27 | 3.44 | 93.33 | 2.86 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.348931322 |
| 89.41 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.3611357204 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.2627857601 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2827773926 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.1030191323 |
| /workspace/coverage/default/12.prim_esc_test.3743718907 |
| /workspace/coverage/default/14.prim_esc_test.1957901286 |
| /workspace/coverage/default/15.prim_esc_test.2723207600 |
| /workspace/coverage/default/16.prim_esc_test.524126724 |
| /workspace/coverage/default/17.prim_esc_test.1757239213 |
| /workspace/coverage/default/18.prim_esc_test.3178655686 |
| /workspace/coverage/default/19.prim_esc_test.1031940310 |
| /workspace/coverage/default/3.prim_esc_test.1285833457 |
| /workspace/coverage/default/4.prim_esc_test.570716623 |
| /workspace/coverage/default/5.prim_esc_test.1441323577 |
| /workspace/coverage/default/6.prim_esc_test.2626144532 |
| /workspace/coverage/default/7.prim_esc_test.1272472052 |
| /workspace/coverage/default/8.prim_esc_test.3744083517 |
| /workspace/coverage/default/9.prim_esc_test.1891559092 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_esc_test.2827773926 | Jul 01 10:28:50 AM PDT 24 | Jul 01 10:28:51 AM PDT 24 | 4206715 ps | ||
| T2 | /workspace/coverage/default/11.prim_esc_test.4000242025 | Jul 01 10:22:33 AM PDT 24 | Jul 01 10:22:34 AM PDT 24 | 4588655 ps | ||
| T3 | /workspace/coverage/default/15.prim_esc_test.2723207600 | Jul 01 10:22:50 AM PDT 24 | Jul 01 10:22:51 AM PDT 24 | 4662270 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.1757239213 | Jul 01 10:28:56 AM PDT 24 | Jul 01 10:28:57 AM PDT 24 | 4784154 ps | ||
| T13 | /workspace/coverage/default/10.prim_esc_test.1030191323 | Jul 01 10:23:51 AM PDT 24 | Jul 01 10:23:52 AM PDT 24 | 4783581 ps | ||
| T4 | /workspace/coverage/default/7.prim_esc_test.1272472052 | Jul 01 10:23:51 AM PDT 24 | Jul 01 10:23:52 AM PDT 24 | 4653987 ps | ||
| T7 | /workspace/coverage/default/1.prim_esc_test.3611357204 | Jul 01 10:28:31 AM PDT 24 | Jul 01 10:28:32 AM PDT 24 | 5584970 ps | ||
| T12 | /workspace/coverage/default/9.prim_esc_test.1891559092 | Jul 01 10:23:02 AM PDT 24 | Jul 01 10:23:02 AM PDT 24 | 4000508 ps | ||
| T14 | /workspace/coverage/default/8.prim_esc_test.3744083517 | Jul 01 10:23:34 AM PDT 24 | Jul 01 10:23:36 AM PDT 24 | 4562762 ps | ||
| T8 | /workspace/coverage/default/13.prim_esc_test.2627857601 | Jul 01 10:23:51 AM PDT 24 | Jul 01 10:23:52 AM PDT 24 | 5116193 ps | ||
| T5 | /workspace/coverage/default/5.prim_esc_test.1441323577 | Jul 01 10:22:31 AM PDT 24 | Jul 01 10:22:32 AM PDT 24 | 4980167 ps | ||
| T10 | /workspace/coverage/default/12.prim_esc_test.3743718907 | Jul 01 10:23:51 AM PDT 24 | Jul 01 10:23:52 AM PDT 24 | 4795900 ps | ||
| T15 | /workspace/coverage/default/3.prim_esc_test.1285833457 | Jul 01 10:30:00 AM PDT 24 | Jul 01 10:30:02 AM PDT 24 | 4328770 ps | ||
| T11 | /workspace/coverage/default/6.prim_esc_test.2626144532 | Jul 01 10:30:00 AM PDT 24 | Jul 01 10:30:02 AM PDT 24 | 4780703 ps | ||
| T9 | /workspace/coverage/default/2.prim_esc_test.348931322 | Jul 01 10:22:27 AM PDT 24 | Jul 01 10:22:28 AM PDT 24 | 4630785 ps | ||
| T16 | /workspace/coverage/default/14.prim_esc_test.1957901286 | Jul 01 10:22:39 AM PDT 24 | Jul 01 10:22:40 AM PDT 24 | 4443542 ps | ||
| T17 | /workspace/coverage/default/19.prim_esc_test.1031940310 | Jul 01 10:23:50 AM PDT 24 | Jul 01 10:23:51 AM PDT 24 | 4652447 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.3178655686 | Jul 01 10:24:24 AM PDT 24 | Jul 01 10:24:26 AM PDT 24 | 4478520 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.570716623 | Jul 01 10:23:51 AM PDT 24 | Jul 01 10:23:52 AM PDT 24 | 5042132 ps | ||
| T20 | /workspace/coverage/default/16.prim_esc_test.524126724 | Jul 01 10:23:39 AM PDT 24 | Jul 01 10:23:39 AM PDT 24 | 5246988 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.4000242025 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4588655 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:22:33 AM PDT 24 |
| Finished | Jul 01 10:22:34 AM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-40af78bc-2ed6-4f08-af5d-e37631cee6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000242025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4000242025 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.348931322 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4630785 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:22:27 AM PDT 24 |
| Finished | Jul 01 10:22:28 AM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-9a810da4-06e5-487a-b52d-92aee36b0ff6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348931322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.348931322 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3611357204 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5584970 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:28:31 AM PDT 24 |
| Finished | Jul 01 10:28:32 AM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-34b8af22-6e4c-4c46-aa67-0cb599531044 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611357204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3611357204 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2627857601 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5116193 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:23:51 AM PDT 24 |
| Finished | Jul 01 10:23:52 AM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-4cc5d3ac-d869-4ebc-98e0-99ce218e1801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627857601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2627857601 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2827773926 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4206715 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:28:50 AM PDT 24 |
| Finished | Jul 01 10:28:51 AM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-64d157bc-e47b-4842-9bf9-11a9731330dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827773926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2827773926 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1030191323 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4783581 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:23:51 AM PDT 24 |
| Finished | Jul 01 10:23:52 AM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-aacf81b3-5271-495e-86c2-201eeffa6d8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030191323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1030191323 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3743718907 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4795900 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:23:51 AM PDT 24 |
| Finished | Jul 01 10:23:52 AM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-fec04283-0f79-40e2-9f80-03ebe6f8b60a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743718907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3743718907 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1957901286 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4443542 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:22:39 AM PDT 24 |
| Finished | Jul 01 10:22:40 AM PDT 24 |
| Peak memory | 146024 kb |
| Host | smart-30366952-d23a-4263-a0dd-7698fefaaa36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957901286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1957901286 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2723207600 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4662270 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:22:50 AM PDT 24 |
| Finished | Jul 01 10:22:51 AM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-9080c3c4-4aee-4d06-9be3-fa1c494fdf48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723207600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2723207600 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.524126724 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5246988 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:23:39 AM PDT 24 |
| Finished | Jul 01 10:23:39 AM PDT 24 |
| Peak memory | 146636 kb |
| Host | smart-5270f373-6fe4-4078-bec9-ee98d2fdb599 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524126724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.524126724 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1757239213 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4784154 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:28:56 AM PDT 24 |
| Finished | Jul 01 10:28:57 AM PDT 24 |
| Peak memory | 146016 kb |
| Host | smart-0a250124-408f-4437-b13f-c7b4885aa5d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757239213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1757239213 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3178655686 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4478520 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:24:24 AM PDT 24 |
| Finished | Jul 01 10:24:26 AM PDT 24 |
| Peak memory | 146120 kb |
| Host | smart-aa133716-4e57-46f4-a53b-56f78ddd7282 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178655686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3178655686 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1031940310 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4652447 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:23:50 AM PDT 24 |
| Finished | Jul 01 10:23:51 AM PDT 24 |
| Peak memory | 145908 kb |
| Host | smart-53b393cf-dc1d-4828-8336-82afe8a76fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031940310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1031940310 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1285833457 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4328770 ps |
| CPU time | 0.36 seconds |
| Started | Jul 01 10:30:00 AM PDT 24 |
| Finished | Jul 01 10:30:02 AM PDT 24 |
| Peak memory | 146692 kb |
| Host | smart-6d8edc30-16e8-4a8e-97ed-e1e0375948bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285833457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1285833457 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.570716623 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5042132 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:23:51 AM PDT 24 |
| Finished | Jul 01 10:23:52 AM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-e2570c06-5fa5-4353-a412-0918d96185fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570716623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.570716623 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1441323577 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4980167 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:22:31 AM PDT 24 |
| Finished | Jul 01 10:22:32 AM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-54314f77-a12b-4156-a2c9-bf1ea73d373f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441323577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1441323577 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2626144532 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4780703 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:30:00 AM PDT 24 |
| Finished | Jul 01 10:30:02 AM PDT 24 |
| Peak memory | 146752 kb |
| Host | smart-ec8a7a8a-8acd-4a5a-a760-01162ca3dfce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626144532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2626144532 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1272472052 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4653987 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:23:51 AM PDT 24 |
| Finished | Jul 01 10:23:52 AM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-1ee417db-b55b-43cc-b816-9648b2878d95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272472052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1272472052 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3744083517 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4562762 ps |
| CPU time | 0.43 seconds |
| Started | Jul 01 10:23:34 AM PDT 24 |
| Finished | Jul 01 10:23:36 AM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-9f5a7f48-55af-4435-a952-8f6d36ac1fdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744083517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3744083517 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1891559092 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4000508 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:23:02 AM PDT 24 |
| Finished | Jul 01 10:23:02 AM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-8ec4da2e-e7bc-4971-b3a0-b14e8e8e5451 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891559092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1891559092 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |