Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.31 85.31 92.38 92.38 78.05 78.05 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/17.prim_esc_test.2076612290
88.27 2.96 93.33 0.95 85.37 7.32 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.2432609417
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/1.prim_esc_test.1196494990
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.2985481454

Tests that do not contribute to grading

Name
/workspace/coverage/default/10.prim_esc_test.4136972705
/workspace/coverage/default/11.prim_esc_test.4223965749
/workspace/coverage/default/12.prim_esc_test.723615238
/workspace/coverage/default/13.prim_esc_test.4013559673
/workspace/coverage/default/14.prim_esc_test.3426913388
/workspace/coverage/default/16.prim_esc_test.262058065
/workspace/coverage/default/18.prim_esc_test.3862282337
/workspace/coverage/default/19.prim_esc_test.4276143582
/workspace/coverage/default/2.prim_esc_test.1235273797
/workspace/coverage/default/3.prim_esc_test.985531445
/workspace/coverage/default/4.prim_esc_test.2535712086
/workspace/coverage/default/5.prim_esc_test.2320058736
/workspace/coverage/default/6.prim_esc_test.3629213842
/workspace/coverage/default/7.prim_esc_test.4085397253
/workspace/coverage/default/8.prim_esc_test.2383998639
/workspace/coverage/default/9.prim_esc_test.1380067745



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_esc_test.4085397253 Jul 01 04:15:58 PM PDT 24 Jul 01 04:16:05 PM PDT 24 4539261 ps
T2 /workspace/coverage/default/8.prim_esc_test.2383998639 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 4886204 ps
T3 /workspace/coverage/default/12.prim_esc_test.723615238 Jul 01 04:15:56 PM PDT 24 Jul 01 04:16:04 PM PDT 24 5010695 ps
T4 /workspace/coverage/default/6.prim_esc_test.3629213842 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 5071233 ps
T5 /workspace/coverage/default/5.prim_esc_test.2320058736 Jul 01 04:15:56 PM PDT 24 Jul 01 04:16:04 PM PDT 24 4826435 ps
T6 /workspace/coverage/default/18.prim_esc_test.3862282337 Jul 01 04:15:58 PM PDT 24 Jul 01 04:16:05 PM PDT 24 4634991 ps
T13 /workspace/coverage/default/2.prim_esc_test.1235273797 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 4888755 ps
T9 /workspace/coverage/default/17.prim_esc_test.2076612290 Jul 01 04:15:56 PM PDT 24 Jul 01 04:16:04 PM PDT 24 5015890 ps
T10 /workspace/coverage/default/14.prim_esc_test.3426913388 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:04 PM PDT 24 4543767 ps
T7 /workspace/coverage/default/19.prim_esc_test.4276143582 Jul 01 04:16:00 PM PDT 24 Jul 01 04:16:06 PM PDT 24 4893617 ps
T8 /workspace/coverage/default/1.prim_esc_test.1196494990 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 4154086 ps
T11 /workspace/coverage/default/15.prim_esc_test.2432609417 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 5116410 ps
T14 /workspace/coverage/default/0.prim_esc_test.2985481454 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:02 PM PDT 24 4622242 ps
T12 /workspace/coverage/default/16.prim_esc_test.262058065 Jul 01 04:15:58 PM PDT 24 Jul 01 04:16:05 PM PDT 24 4703997 ps
T15 /workspace/coverage/default/11.prim_esc_test.4223965749 Jul 01 04:15:57 PM PDT 24 Jul 01 04:16:05 PM PDT 24 5003254 ps
T16 /workspace/coverage/default/4.prim_esc_test.2535712086 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 4257581 ps
T17 /workspace/coverage/default/13.prim_esc_test.4013559673 Jul 01 04:15:56 PM PDT 24 Jul 01 04:16:04 PM PDT 24 4928377 ps
T18 /workspace/coverage/default/3.prim_esc_test.985531445 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:03 PM PDT 24 4530171 ps
T19 /workspace/coverage/default/9.prim_esc_test.1380067745 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 4901237 ps
T20 /workspace/coverage/default/10.prim_esc_test.4136972705 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 4497440 ps

Test location /workspace/coverage/default/17.prim_esc_test.2076612290
Short name T9
Test name
Test status
Simulation time 5015890 ps
CPU time 0.37 seconds
Started Jul 01 04:15:56 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 146200 kb
Host smart-d4d2c40b-1d6d-4e51-8d14-61e8e5bef692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076612290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2076612290
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2432609417
Short name T11
Test name
Test status
Simulation time 5116410 ps
CPU time 0.38 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 146276 kb
Host smart-1d6e96e5-9379-4c48-aea1-b165a4568bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432609417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2432609417
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.1196494990
Short name T8
Test name
Test status
Simulation time 4154086 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 146276 kb
Host smart-65deac23-ccdd-4e31-8351-1171b51ec2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196494990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1196494990
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2985481454
Short name T14
Test name
Test status
Simulation time 4622242 ps
CPU time 0.37 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 146276 kb
Host smart-c689a328-9a82-4c35-a032-87ae0fb1c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985481454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2985481454
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.4136972705
Short name T20
Test name
Test status
Simulation time 4497440 ps
CPU time 0.37 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 146276 kb
Host smart-a8c810e2-6439-40d0-b377-b8436c3ab9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136972705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4136972705
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.4223965749
Short name T15
Test name
Test status
Simulation time 5003254 ps
CPU time 0.39 seconds
Started Jul 01 04:15:57 PM PDT 24
Finished Jul 01 04:16:05 PM PDT 24
Peak memory 146184 kb
Host smart-035ec047-ee71-44f8-87d3-b60cf9d5adc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223965749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4223965749
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.723615238
Short name T3
Test name
Test status
Simulation time 5010695 ps
CPU time 0.38 seconds
Started Jul 01 04:15:56 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 146164 kb
Host smart-2fb9c318-a1f8-4553-9f2b-86de3a0fc281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723615238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.723615238
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.4013559673
Short name T17
Test name
Test status
Simulation time 4928377 ps
CPU time 0.38 seconds
Started Jul 01 04:15:56 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 146200 kb
Host smart-c0b01be3-e50b-4666-a1f8-d6fdbb6ec4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013559673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4013559673
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3426913388
Short name T10
Test name
Test status
Simulation time 4543767 ps
CPU time 0.38 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 146200 kb
Host smart-1266e833-0518-448c-bdb8-18b264f29a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426913388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3426913388
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.262058065
Short name T12
Test name
Test status
Simulation time 4703997 ps
CPU time 0.37 seconds
Started Jul 01 04:15:58 PM PDT 24
Finished Jul 01 04:16:05 PM PDT 24
Peak memory 146212 kb
Host smart-ff8cb546-aae2-4719-9172-be3b432c8944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262058065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.262058065
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3862282337
Short name T6
Test name
Test status
Simulation time 4634991 ps
CPU time 0.39 seconds
Started Jul 01 04:15:58 PM PDT 24
Finished Jul 01 04:16:05 PM PDT 24
Peak memory 146232 kb
Host smart-fba4c8e4-a4c9-47dd-a3da-a6389b7717dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862282337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3862282337
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.4276143582
Short name T7
Test name
Test status
Simulation time 4893617 ps
CPU time 0.37 seconds
Started Jul 01 04:16:00 PM PDT 24
Finished Jul 01 04:16:06 PM PDT 24
Peak memory 146248 kb
Host smart-88de682e-538c-46fd-b3ed-b65e7b467c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276143582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4276143582
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1235273797
Short name T13
Test name
Test status
Simulation time 4888755 ps
CPU time 0.37 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 146276 kb
Host smart-1ebbc170-9253-45c5-8aa9-322d78c38098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235273797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1235273797
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.985531445
Short name T18
Test name
Test status
Simulation time 4530171 ps
CPU time 0.38 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:03 PM PDT 24
Peak memory 146232 kb
Host smart-9111a05f-95e3-43bd-bc35-ec58a6f7f864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985531445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.985531445
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2535712086
Short name T16
Test name
Test status
Simulation time 4257581 ps
CPU time 0.39 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 146276 kb
Host smart-924c42c3-a4af-49dc-9837-d733a22ff129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535712086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2535712086
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.2320058736
Short name T5
Test name
Test status
Simulation time 4826435 ps
CPU time 0.4 seconds
Started Jul 01 04:15:56 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 146248 kb
Host smart-5e7afb27-0523-43ed-92c4-d9be5851b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320058736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2320058736
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.3629213842
Short name T4
Test name
Test status
Simulation time 5071233 ps
CPU time 0.38 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 146248 kb
Host smart-2ded2553-9395-4eea-907e-5856422e7977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629213842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3629213842
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.4085397253
Short name T1
Test name
Test status
Simulation time 4539261 ps
CPU time 0.37 seconds
Started Jul 01 04:15:58 PM PDT 24
Finished Jul 01 04:16:05 PM PDT 24
Peak memory 146144 kb
Host smart-5578bbf3-aef5-49e9-b53e-59a6eb2c3bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085397253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4085397253
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.2383998639
Short name T2
Test name
Test status
Simulation time 4886204 ps
CPU time 0.38 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 146276 kb
Host smart-5a0784af-0e78-4ec0-b0b5-1d11db59d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383998639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2383998639
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.1380067745
Short name T19
Test name
Test status
Simulation time 4901237 ps
CPU time 0.37 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 146248 kb
Host smart-c50c3164-4b7a-408e-81a2-28bcada7aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380067745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1380067745
Directory /workspace/9.prim_esc_test/latest
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