Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.53 86.53 92.38 92.38 85.37 85.37 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/8.prim_esc_test.1633687424
88.27 1.74 93.33 0.95 85.37 0.00 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/14.prim_esc_test.3332413183
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.3703953874
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.238424922

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.1478209649
/workspace/coverage/default/1.prim_esc_test.3194210028
/workspace/coverage/default/10.prim_esc_test.805413436
/workspace/coverage/default/12.prim_esc_test.1982978509
/workspace/coverage/default/13.prim_esc_test.2207951273
/workspace/coverage/default/16.prim_esc_test.1568369804
/workspace/coverage/default/17.prim_esc_test.2321397351
/workspace/coverage/default/18.prim_esc_test.2997671860
/workspace/coverage/default/19.prim_esc_test.1724770404
/workspace/coverage/default/2.prim_esc_test.1595860325
/workspace/coverage/default/3.prim_esc_test.2498867856
/workspace/coverage/default/4.prim_esc_test.3609553232
/workspace/coverage/default/5.prim_esc_test.3529251055
/workspace/coverage/default/6.prim_esc_test.2614587478
/workspace/coverage/default/7.prim_esc_test.437002038
/workspace/coverage/default/9.prim_esc_test.3009343940



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_esc_test.805413436 Jul 02 07:31:52 AM PDT 24 Jul 02 07:31:53 AM PDT 24 4149595 ps
T2 /workspace/coverage/default/9.prim_esc_test.3009343940 Jul 02 07:33:48 AM PDT 24 Jul 02 07:33:49 AM PDT 24 4845147 ps
T3 /workspace/coverage/default/16.prim_esc_test.1568369804 Jul 02 07:36:42 AM PDT 24 Jul 02 07:36:49 AM PDT 24 5437655 ps
T4 /workspace/coverage/default/2.prim_esc_test.1595860325 Jul 02 07:36:31 AM PDT 24 Jul 02 07:36:38 AM PDT 24 4416860 ps
T7 /workspace/coverage/default/7.prim_esc_test.437002038 Jul 02 07:36:34 AM PDT 24 Jul 02 07:36:42 AM PDT 24 4891463 ps
T5 /workspace/coverage/default/11.prim_esc_test.238424922 Jul 02 07:36:35 AM PDT 24 Jul 02 07:36:43 AM PDT 24 5074939 ps
T6 /workspace/coverage/default/1.prim_esc_test.3194210028 Jul 02 07:36:32 AM PDT 24 Jul 02 07:36:39 AM PDT 24 4599722 ps
T14 /workspace/coverage/default/5.prim_esc_test.3529251055 Jul 02 07:36:34 AM PDT 24 Jul 02 07:36:42 AM PDT 24 4480379 ps
T15 /workspace/coverage/default/15.prim_esc_test.3703953874 Jul 02 07:32:31 AM PDT 24 Jul 02 07:32:32 AM PDT 24 4600192 ps
T10 /workspace/coverage/default/8.prim_esc_test.1633687424 Jul 02 07:34:47 AM PDT 24 Jul 02 07:34:48 AM PDT 24 4866849 ps
T16 /workspace/coverage/default/13.prim_esc_test.2207951273 Jul 02 07:36:45 AM PDT 24 Jul 02 07:36:52 AM PDT 24 5145532 ps
T12 /workspace/coverage/default/17.prim_esc_test.2321397351 Jul 02 07:32:15 AM PDT 24 Jul 02 07:32:16 AM PDT 24 4708204 ps
T11 /workspace/coverage/default/6.prim_esc_test.2614587478 Jul 02 07:36:31 AM PDT 24 Jul 02 07:36:38 AM PDT 24 5020796 ps
T13 /workspace/coverage/default/14.prim_esc_test.3332413183 Jul 02 07:36:43 AM PDT 24 Jul 02 07:36:51 AM PDT 24 4848775 ps
T18 /workspace/coverage/default/18.prim_esc_test.2997671860 Jul 02 07:36:45 AM PDT 24 Jul 02 07:36:52 AM PDT 24 5006689 ps
T8 /workspace/coverage/default/19.prim_esc_test.1724770404 Jul 02 07:36:43 AM PDT 24 Jul 02 07:36:51 AM PDT 24 4811661 ps
T19 /workspace/coverage/default/0.prim_esc_test.1478209649 Jul 02 07:36:32 AM PDT 24 Jul 02 07:36:39 AM PDT 24 5188218 ps
T9 /workspace/coverage/default/12.prim_esc_test.1982978509 Jul 02 07:36:32 AM PDT 24 Jul 02 07:36:39 AM PDT 24 4776732 ps
T17 /workspace/coverage/default/4.prim_esc_test.3609553232 Jul 02 07:36:32 AM PDT 24 Jul 02 07:36:39 AM PDT 24 4568461 ps
T20 /workspace/coverage/default/3.prim_esc_test.2498867856 Jul 02 07:36:31 AM PDT 24 Jul 02 07:36:38 AM PDT 24 4547798 ps

Test location /workspace/coverage/default/8.prim_esc_test.1633687424
Short name T10
Test name
Test status
Simulation time 4866849 ps
CPU time 0.39 seconds
Started Jul 02 07:34:47 AM PDT 24
Finished Jul 02 07:34:48 AM PDT 24
Peak memory 145992 kb
Host smart-7f8faf69-fa89-407f-a93b-01a4966e3200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633687424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1633687424
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3332413183
Short name T13
Test name
Test status
Simulation time 4848775 ps
CPU time 0.37 seconds
Started Jul 02 07:36:43 AM PDT 24
Finished Jul 02 07:36:51 AM PDT 24
Peak memory 145752 kb
Host smart-25d8caf7-df05-4490-863b-e46d436b49b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332413183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3332413183
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3703953874
Short name T15
Test name
Test status
Simulation time 4600192 ps
CPU time 0.38 seconds
Started Jul 02 07:32:31 AM PDT 24
Finished Jul 02 07:32:32 AM PDT 24
Peak memory 146280 kb
Host smart-2e676b9f-f3d7-48a7-bff9-eadeb431c614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703953874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3703953874
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.238424922
Short name T5
Test name
Test status
Simulation time 5074939 ps
CPU time 0.37 seconds
Started Jul 02 07:36:35 AM PDT 24
Finished Jul 02 07:36:43 AM PDT 24
Peak memory 145536 kb
Host smart-af277426-aaf6-4ed5-b403-8e60ec3f6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238424922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.238424922
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.1478209649
Short name T19
Test name
Test status
Simulation time 5188218 ps
CPU time 0.38 seconds
Started Jul 02 07:36:32 AM PDT 24
Finished Jul 02 07:36:39 AM PDT 24
Peak memory 145456 kb
Host smart-7c0f1fe7-6639-41ce-8576-07ef20be87dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478209649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1478209649
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3194210028
Short name T6
Test name
Test status
Simulation time 4599722 ps
CPU time 0.37 seconds
Started Jul 02 07:36:32 AM PDT 24
Finished Jul 02 07:36:39 AM PDT 24
Peak memory 145456 kb
Host smart-ea1405f6-5de8-4bdb-9b06-1266724efe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194210028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3194210028
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.805413436
Short name T1
Test name
Test status
Simulation time 4149595 ps
CPU time 0.42 seconds
Started Jul 02 07:31:52 AM PDT 24
Finished Jul 02 07:31:53 AM PDT 24
Peak memory 145720 kb
Host smart-5405057c-01c3-4fe5-9794-d0c7527a62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805413436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.805413436
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.1982978509
Short name T9
Test name
Test status
Simulation time 4776732 ps
CPU time 0.36 seconds
Started Jul 02 07:36:32 AM PDT 24
Finished Jul 02 07:36:39 AM PDT 24
Peak memory 145500 kb
Host smart-ac13c9d5-54f4-43b0-a66d-7d090249913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982978509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1982978509
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2207951273
Short name T16
Test name
Test status
Simulation time 5145532 ps
CPU time 0.38 seconds
Started Jul 02 07:36:45 AM PDT 24
Finished Jul 02 07:36:52 AM PDT 24
Peak memory 144980 kb
Host smart-0bd68d66-9a14-4f00-b245-941f5597d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207951273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2207951273
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1568369804
Short name T3
Test name
Test status
Simulation time 5437655 ps
CPU time 0.37 seconds
Started Jul 02 07:36:42 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 145608 kb
Host smart-b8553191-d619-440a-9135-07c6f0c5390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568369804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1568369804
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2321397351
Short name T12
Test name
Test status
Simulation time 4708204 ps
CPU time 0.38 seconds
Started Jul 02 07:32:15 AM PDT 24
Finished Jul 02 07:32:16 AM PDT 24
Peak memory 146032 kb
Host smart-8df0ca30-f94d-48db-b213-f611dec3a001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321397351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2321397351
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2997671860
Short name T18
Test name
Test status
Simulation time 5006689 ps
CPU time 0.38 seconds
Started Jul 02 07:36:45 AM PDT 24
Finished Jul 02 07:36:52 AM PDT 24
Peak memory 144972 kb
Host smart-fc0f1f16-c7de-428c-b783-48e6a7b7aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997671860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2997671860
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1724770404
Short name T8
Test name
Test status
Simulation time 4811661 ps
CPU time 0.37 seconds
Started Jul 02 07:36:43 AM PDT 24
Finished Jul 02 07:36:51 AM PDT 24
Peak memory 145752 kb
Host smart-edcab75c-7512-4c49-b0ea-a8e7edf00a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724770404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1724770404
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1595860325
Short name T4
Test name
Test status
Simulation time 4416860 ps
CPU time 0.44 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 145016 kb
Host smart-369b9222-634d-4844-85f8-897bab6b2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595860325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1595860325
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2498867856
Short name T20
Test name
Test status
Simulation time 4547798 ps
CPU time 0.4 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 144732 kb
Host smart-f18d2b29-fe45-4cec-9752-05b0c75b05f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498867856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2498867856
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3609553232
Short name T17
Test name
Test status
Simulation time 4568461 ps
CPU time 0.36 seconds
Started Jul 02 07:36:32 AM PDT 24
Finished Jul 02 07:36:39 AM PDT 24
Peak memory 145392 kb
Host smart-3eefc0ab-e93c-49b9-a6bf-4d007ffe29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609553232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3609553232
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3529251055
Short name T14
Test name
Test status
Simulation time 4480379 ps
CPU time 0.52 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 144612 kb
Host smart-f9576d1a-7d34-4212-a6d7-b18f28b39166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529251055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3529251055
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2614587478
Short name T11
Test name
Test status
Simulation time 5020796 ps
CPU time 0.42 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 144936 kb
Host smart-e8710f37-4c8a-4d3f-948b-0df831c279da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614587478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2614587478
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.437002038
Short name T7
Test name
Test status
Simulation time 4891463 ps
CPU time 0.39 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 144484 kb
Host smart-febebf21-eed3-4dd3-a03e-cc0cb1d9bdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437002038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.437002038
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3009343940
Short name T2
Test name
Test status
Simulation time 4845147 ps
CPU time 0.37 seconds
Started Jul 02 07:33:48 AM PDT 24
Finished Jul 02 07:33:49 AM PDT 24
Peak memory 146080 kb
Host smart-537c5b89-29a0-4983-b611-e952113b51dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009343940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3009343940
Directory /workspace/9.prim_esc_test/latest
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