Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.94 85.94 92.38 92.38 85.37 85.37 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/15.prim_esc_test.2006150852
88.27 2.33 93.33 0.95 85.37 0.00 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/7.prim_esc_test.702596829
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/12.prim_esc_test.991397274
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/1.prim_esc_test.3134762333

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.3227317639
/workspace/coverage/default/10.prim_esc_test.457771100
/workspace/coverage/default/11.prim_esc_test.3011737235
/workspace/coverage/default/13.prim_esc_test.2599800646
/workspace/coverage/default/14.prim_esc_test.2675288613
/workspace/coverage/default/16.prim_esc_test.486069235
/workspace/coverage/default/17.prim_esc_test.3824360535
/workspace/coverage/default/18.prim_esc_test.1845060901
/workspace/coverage/default/19.prim_esc_test.2505696315
/workspace/coverage/default/2.prim_esc_test.2044892305
/workspace/coverage/default/3.prim_esc_test.2818162916
/workspace/coverage/default/4.prim_esc_test.2596708942
/workspace/coverage/default/5.prim_esc_test.775495971
/workspace/coverage/default/6.prim_esc_test.2687382427
/workspace/coverage/default/8.prim_esc_test.2156329195
/workspace/coverage/default/9.prim_esc_test.3864779794



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_esc_test.2675288613 Jul 03 04:19:55 PM PDT 24 Jul 03 04:19:56 PM PDT 24 5103323 ps
T2 /workspace/coverage/default/13.prim_esc_test.2599800646 Jul 03 04:20:54 PM PDT 24 Jul 03 04:20:56 PM PDT 24 5217162 ps
T3 /workspace/coverage/default/12.prim_esc_test.991397274 Jul 03 04:21:09 PM PDT 24 Jul 03 04:21:09 PM PDT 24 4819595 ps
T4 /workspace/coverage/default/18.prim_esc_test.1845060901 Jul 03 04:20:56 PM PDT 24 Jul 03 04:20:57 PM PDT 24 4283930 ps
T6 /workspace/coverage/default/10.prim_esc_test.457771100 Jul 03 04:20:56 PM PDT 24 Jul 03 04:20:56 PM PDT 24 4510230 ps
T12 /workspace/coverage/default/19.prim_esc_test.2505696315 Jul 03 04:20:23 PM PDT 24 Jul 03 04:20:24 PM PDT 24 4606144 ps
T7 /workspace/coverage/default/15.prim_esc_test.2006150852 Jul 03 04:20:54 PM PDT 24 Jul 03 04:20:56 PM PDT 24 4859101 ps
T13 /workspace/coverage/default/6.prim_esc_test.2687382427 Jul 03 04:21:03 PM PDT 24 Jul 03 04:21:04 PM PDT 24 4679306 ps
T10 /workspace/coverage/default/5.prim_esc_test.775495971 Jul 03 04:21:03 PM PDT 24 Jul 03 04:21:04 PM PDT 24 4529686 ps
T14 /workspace/coverage/default/3.prim_esc_test.2818162916 Jul 03 04:22:31 PM PDT 24 Jul 03 04:22:32 PM PDT 24 4328664 ps
T16 /workspace/coverage/default/9.prim_esc_test.3864779794 Jul 03 04:21:03 PM PDT 24 Jul 03 04:21:04 PM PDT 24 4489213 ps
T8 /workspace/coverage/default/17.prim_esc_test.3824360535 Jul 03 04:21:09 PM PDT 24 Jul 03 04:21:09 PM PDT 24 4741075 ps
T9 /workspace/coverage/default/0.prim_esc_test.3227317639 Jul 03 04:21:06 PM PDT 24 Jul 03 04:21:08 PM PDT 24 4615653 ps
T17 /workspace/coverage/default/11.prim_esc_test.3011737235 Jul 03 04:21:09 PM PDT 24 Jul 03 04:21:09 PM PDT 24 4976908 ps
T18 /workspace/coverage/default/16.prim_esc_test.486069235 Jul 03 04:20:56 PM PDT 24 Jul 03 04:20:56 PM PDT 24 4945337 ps
T15 /workspace/coverage/default/4.prim_esc_test.2596708942 Jul 03 04:21:09 PM PDT 24 Jul 03 04:21:09 PM PDT 24 4529187 ps
T11 /workspace/coverage/default/7.prim_esc_test.702596829 Jul 03 04:22:07 PM PDT 24 Jul 03 04:22:09 PM PDT 24 5102918 ps
T19 /workspace/coverage/default/8.prim_esc_test.2156329195 Jul 03 04:21:07 PM PDT 24 Jul 03 04:21:08 PM PDT 24 4308003 ps
T20 /workspace/coverage/default/2.prim_esc_test.2044892305 Jul 03 04:22:40 PM PDT 24 Jul 03 04:22:41 PM PDT 24 4836850 ps
T5 /workspace/coverage/default/1.prim_esc_test.3134762333 Jul 03 04:19:03 PM PDT 24 Jul 03 04:19:04 PM PDT 24 4951641 ps

Test location /workspace/coverage/default/15.prim_esc_test.2006150852
Short name T7
Test name
Test status
Simulation time 4859101 ps
CPU time 0.43 seconds
Started Jul 03 04:20:54 PM PDT 24
Finished Jul 03 04:20:56 PM PDT 24
Peak memory 145016 kb
Host smart-595cadb8-b986-4e45-b612-388bd1057c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006150852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2006150852
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.702596829
Short name T11
Test name
Test status
Simulation time 5102918 ps
CPU time 0.43 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:22:09 PM PDT 24
Peak memory 146376 kb
Host smart-fdc69042-c235-40de-bdaf-b1d9ec99760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702596829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.702596829
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.991397274
Short name T3
Test name
Test status
Simulation time 4819595 ps
CPU time 0.38 seconds
Started Jul 03 04:21:09 PM PDT 24
Finished Jul 03 04:21:09 PM PDT 24
Peak memory 145612 kb
Host smart-779d07d0-bbe1-4ab2-9a62-6faa68042d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991397274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.991397274
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3134762333
Short name T5
Test name
Test status
Simulation time 4951641 ps
CPU time 0.43 seconds
Started Jul 03 04:19:03 PM PDT 24
Finished Jul 03 04:19:04 PM PDT 24
Peak memory 145992 kb
Host smart-8a3cc8a5-198f-40c4-844c-23a03ed45e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134762333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3134762333
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3227317639
Short name T9
Test name
Test status
Simulation time 4615653 ps
CPU time 0.43 seconds
Started Jul 03 04:21:06 PM PDT 24
Finished Jul 03 04:21:08 PM PDT 24
Peak memory 145768 kb
Host smart-7785e15c-3a79-4161-88d6-bab3c4207e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227317639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3227317639
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.457771100
Short name T6
Test name
Test status
Simulation time 4510230 ps
CPU time 0.4 seconds
Started Jul 03 04:20:56 PM PDT 24
Finished Jul 03 04:20:56 PM PDT 24
Peak memory 145696 kb
Host smart-9bae81c2-cc57-496a-b00c-e9f1ae9195a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457771100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.457771100
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.3011737235
Short name T17
Test name
Test status
Simulation time 4976908 ps
CPU time 0.39 seconds
Started Jul 03 04:21:09 PM PDT 24
Finished Jul 03 04:21:09 PM PDT 24
Peak memory 145684 kb
Host smart-9baeb3a8-2266-4b77-bf5d-7f2eaee73a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011737235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3011737235
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2599800646
Short name T2
Test name
Test status
Simulation time 5217162 ps
CPU time 0.4 seconds
Started Jul 03 04:20:54 PM PDT 24
Finished Jul 03 04:20:56 PM PDT 24
Peak memory 145528 kb
Host smart-4b0d8ebe-1cf9-4438-8158-686158df914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599800646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2599800646
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2675288613
Short name T1
Test name
Test status
Simulation time 5103323 ps
CPU time 0.39 seconds
Started Jul 03 04:19:55 PM PDT 24
Finished Jul 03 04:19:56 PM PDT 24
Peak memory 145996 kb
Host smart-2e01eafc-83fc-4cd8-bb6d-9470cfe3c12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675288613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2675288613
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.486069235
Short name T18
Test name
Test status
Simulation time 4945337 ps
CPU time 0.39 seconds
Started Jul 03 04:20:56 PM PDT 24
Finished Jul 03 04:20:56 PM PDT 24
Peak memory 145700 kb
Host smart-a529d49d-76eb-49c6-ad2d-7bd0a5f96e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486069235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.486069235
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3824360535
Short name T8
Test name
Test status
Simulation time 4741075 ps
CPU time 0.39 seconds
Started Jul 03 04:21:09 PM PDT 24
Finished Jul 03 04:21:09 PM PDT 24
Peak memory 145684 kb
Host smart-a6f0b27d-354a-4ed4-bb4b-fa2223ca92d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824360535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3824360535
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1845060901
Short name T4
Test name
Test status
Simulation time 4283930 ps
CPU time 0.37 seconds
Started Jul 03 04:20:56 PM PDT 24
Finished Jul 03 04:20:57 PM PDT 24
Peak memory 145684 kb
Host smart-9a0e95b2-0722-459b-8fda-c2335b3e615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845060901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1845060901
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2505696315
Short name T12
Test name
Test status
Simulation time 4606144 ps
CPU time 0.38 seconds
Started Jul 03 04:20:23 PM PDT 24
Finished Jul 03 04:20:24 PM PDT 24
Peak memory 145740 kb
Host smart-077e0d60-026f-4e0f-9854-c0a92c29885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505696315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2505696315
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2044892305
Short name T20
Test name
Test status
Simulation time 4836850 ps
CPU time 0.38 seconds
Started Jul 03 04:22:40 PM PDT 24
Finished Jul 03 04:22:41 PM PDT 24
Peak memory 145708 kb
Host smart-097b3c33-6081-4c27-ac56-eec29604db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044892305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2044892305
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2818162916
Short name T14
Test name
Test status
Simulation time 4328664 ps
CPU time 0.37 seconds
Started Jul 03 04:22:31 PM PDT 24
Finished Jul 03 04:22:32 PM PDT 24
Peak memory 145708 kb
Host smart-d6b2fa60-7c48-4d03-82de-dff59cc110a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818162916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2818162916
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2596708942
Short name T15
Test name
Test status
Simulation time 4529187 ps
CPU time 0.38 seconds
Started Jul 03 04:21:09 PM PDT 24
Finished Jul 03 04:21:09 PM PDT 24
Peak memory 145540 kb
Host smart-7110506a-f81c-45b2-bedf-ec1e06ac4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596708942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2596708942
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.775495971
Short name T10
Test name
Test status
Simulation time 4529686 ps
CPU time 0.43 seconds
Started Jul 03 04:21:03 PM PDT 24
Finished Jul 03 04:21:04 PM PDT 24
Peak memory 146376 kb
Host smart-3c26fc5c-bae9-4d51-a2d8-79b1b826d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775495971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.775495971
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2687382427
Short name T13
Test name
Test status
Simulation time 4679306 ps
CPU time 0.39 seconds
Started Jul 03 04:21:03 PM PDT 24
Finished Jul 03 04:21:04 PM PDT 24
Peak memory 145936 kb
Host smart-97f9c03b-fa77-45a6-a172-6a7f3d6986dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687382427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2687382427
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.2156329195
Short name T19
Test name
Test status
Simulation time 4308003 ps
CPU time 0.38 seconds
Started Jul 03 04:21:07 PM PDT 24
Finished Jul 03 04:21:08 PM PDT 24
Peak memory 145028 kb
Host smart-fa0fbb44-3ec7-4f4d-80f8-b2a3233c809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156329195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2156329195
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3864779794
Short name T16
Test name
Test status
Simulation time 4489213 ps
CPU time 0.42 seconds
Started Jul 03 04:21:03 PM PDT 24
Finished Jul 03 04:21:04 PM PDT 24
Peak memory 144896 kb
Host smart-1e64afa0-f8d4-4ece-9583-518e65da9109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864779794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3864779794
Directory /workspace/9.prim_esc_test/latest
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