| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.94 | 85.94 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/9.prim_esc_test.1173241700 |
| 88.27 | 2.33 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1649885524 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.2069595702 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.3407703436 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1163434288 |
| /workspace/coverage/default/1.prim_esc_test.3857513886 |
| /workspace/coverage/default/10.prim_esc_test.1832410049 |
| /workspace/coverage/default/11.prim_esc_test.2078349719 |
| /workspace/coverage/default/12.prim_esc_test.1511054899 |
| /workspace/coverage/default/13.prim_esc_test.982112635 |
| /workspace/coverage/default/15.prim_esc_test.1293872286 |
| /workspace/coverage/default/16.prim_esc_test.1923922587 |
| /workspace/coverage/default/17.prim_esc_test.1314548552 |
| /workspace/coverage/default/18.prim_esc_test.108037821 |
| /workspace/coverage/default/19.prim_esc_test.48921164 |
| /workspace/coverage/default/3.prim_esc_test.945632186 |
| /workspace/coverage/default/4.prim_esc_test.3007357883 |
| /workspace/coverage/default/5.prim_esc_test.2668668113 |
| /workspace/coverage/default/6.prim_esc_test.2027534948 |
| /workspace/coverage/default/8.prim_esc_test.638392510 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_esc_test.108037821 | Jul 04 04:48:22 PM PDT 24 | Jul 04 04:48:23 PM PDT 24 | 4894740 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.2069595702 | Jul 04 04:48:20 PM PDT 24 | Jul 04 04:48:21 PM PDT 24 | 4836384 ps | ||
| T3 | /workspace/coverage/default/12.prim_esc_test.1511054899 | Jul 04 04:48:06 PM PDT 24 | Jul 04 04:48:07 PM PDT 24 | 4804367 ps | ||
| T4 | /workspace/coverage/default/9.prim_esc_test.1173241700 | Jul 04 04:48:20 PM PDT 24 | Jul 04 04:48:21 PM PDT 24 | 4734578 ps | ||
| T14 | /workspace/coverage/default/10.prim_esc_test.1832410049 | Jul 04 04:48:13 PM PDT 24 | Jul 04 04:48:14 PM PDT 24 | 4672913 ps | ||
| T6 | /workspace/coverage/default/5.prim_esc_test.2668668113 | Jul 04 04:48:15 PM PDT 24 | Jul 04 04:48:21 PM PDT 24 | 5202087 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.2078349719 | Jul 04 04:48:17 PM PDT 24 | Jul 04 04:48:18 PM PDT 24 | 5065150 ps | ||
| T16 | /workspace/coverage/default/3.prim_esc_test.945632186 | Jul 04 04:48:10 PM PDT 24 | Jul 04 04:48:11 PM PDT 24 | 4631754 ps | ||
| T17 | /workspace/coverage/default/0.prim_esc_test.1163434288 | Jul 04 04:48:09 PM PDT 24 | Jul 04 04:48:10 PM PDT 24 | 4852424 ps | ||
| T7 | /workspace/coverage/default/19.prim_esc_test.48921164 | Jul 04 04:48:22 PM PDT 24 | Jul 04 04:48:22 PM PDT 24 | 4281772 ps | ||
| T12 | /workspace/coverage/default/4.prim_esc_test.3007357883 | Jul 04 04:48:15 PM PDT 24 | Jul 04 04:48:19 PM PDT 24 | 4702599 ps | ||
| T18 | /workspace/coverage/default/1.prim_esc_test.3857513886 | Jul 04 04:48:15 PM PDT 24 | Jul 04 04:48:16 PM PDT 24 | 4342335 ps | ||
| T10 | /workspace/coverage/default/8.prim_esc_test.638392510 | Jul 04 04:48:19 PM PDT 24 | Jul 04 04:48:20 PM PDT 24 | 4393476 ps | ||
| T8 | /workspace/coverage/default/14.prim_esc_test.1649885524 | Jul 04 04:48:14 PM PDT 24 | Jul 04 04:48:15 PM PDT 24 | 4651819 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.982112635 | Jul 04 04:48:23 PM PDT 24 | Jul 04 04:48:24 PM PDT 24 | 5133741 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.1293872286 | Jul 04 04:48:29 PM PDT 24 | Jul 04 04:48:30 PM PDT 24 | 4812203 ps | ||
| T5 | /workspace/coverage/default/16.prim_esc_test.1923922587 | Jul 04 04:48:22 PM PDT 24 | Jul 04 04:48:22 PM PDT 24 | 4988955 ps | ||
| T9 | /workspace/coverage/default/7.prim_esc_test.3407703436 | Jul 04 04:48:33 PM PDT 24 | Jul 04 04:48:34 PM PDT 24 | 4575190 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.1314548552 | Jul 04 04:48:16 PM PDT 24 | Jul 04 04:48:17 PM PDT 24 | 4458742 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.2027534948 | Jul 04 04:48:23 PM PDT 24 | Jul 04 04:48:24 PM PDT 24 | 4273143 ps |
| Test location | /workspace/coverage/default/9.prim_esc_test.1173241700 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4734578 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:20 PM PDT 24 |
| Finished | Jul 04 04:48:21 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-11264a70-8d2b-4d96-ae55-13fe74279ca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1173241700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1173241700 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1649885524 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4651819 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:14 PM PDT 24 |
| Finished | Jul 04 04:48:15 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-b15cf3e2-abe9-487f-9f18-fb5738251f42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649885524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1649885524 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2069595702 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4836384 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:20 PM PDT 24 |
| Finished | Jul 04 04:48:21 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-7d3205cc-4ea3-4c4d-8463-d323531dbaf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069595702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2069595702 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3407703436 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4575190 ps |
| CPU time | 0.36 seconds |
| Started | Jul 04 04:48:33 PM PDT 24 |
| Finished | Jul 04 04:48:34 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-d6ae541a-9bd7-4a12-9acc-6de3192633bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407703436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3407703436 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1163434288 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4852424 ps |
| CPU time | 0.36 seconds |
| Started | Jul 04 04:48:09 PM PDT 24 |
| Finished | Jul 04 04:48:10 PM PDT 24 |
| Peak memory | 146040 kb |
| Host | smart-5016b56b-da01-486b-8897-a4c8c07e9cb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163434288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1163434288 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3857513886 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4342335 ps |
| CPU time | 0.36 seconds |
| Started | Jul 04 04:48:15 PM PDT 24 |
| Finished | Jul 04 04:48:16 PM PDT 24 |
| Peak memory | 146040 kb |
| Host | smart-143db2c7-7c08-44c8-986e-0499fc529ea7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857513886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3857513886 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1832410049 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4672913 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:13 PM PDT 24 |
| Finished | Jul 04 04:48:14 PM PDT 24 |
| Peak memory | 146076 kb |
| Host | smart-217074b4-7756-47a6-9d84-954b62668b84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832410049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1832410049 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2078349719 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5065150 ps |
| CPU time | 0.37 seconds |
| Started | Jul 04 04:48:17 PM PDT 24 |
| Finished | Jul 04 04:48:18 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-75062c78-2098-40e0-a70c-1a5261ff84cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078349719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2078349719 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1511054899 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4804367 ps |
| CPU time | 0.37 seconds |
| Started | Jul 04 04:48:06 PM PDT 24 |
| Finished | Jul 04 04:48:07 PM PDT 24 |
| Peak memory | 146356 kb |
| Host | smart-1c08664e-a537-4fed-ac27-228a8a8baf08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511054899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1511054899 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.982112635 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5133741 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:23 PM PDT 24 |
| Finished | Jul 04 04:48:24 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-7b9a2499-b728-40b2-a867-b3ab007a43f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982112635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.982112635 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1293872286 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4812203 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:29 PM PDT 24 |
| Finished | Jul 04 04:48:30 PM PDT 24 |
| Peak memory | 145992 kb |
| Host | smart-e10a3b76-9917-4c12-9472-359c555713ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293872286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1293872286 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1923922587 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4988955 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:22 PM PDT 24 |
| Finished | Jul 04 04:48:22 PM PDT 24 |
| Peak memory | 146124 kb |
| Host | smart-a6065b6e-66eb-4e8d-8a47-94f239a859b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923922587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1923922587 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1314548552 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4458742 ps |
| CPU time | 0.36 seconds |
| Started | Jul 04 04:48:16 PM PDT 24 |
| Finished | Jul 04 04:48:17 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-32b44c7e-5161-41f4-a582-3fc9c8a59861 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314548552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1314548552 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.108037821 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4894740 ps |
| CPU time | 0.41 seconds |
| Started | Jul 04 04:48:22 PM PDT 24 |
| Finished | Jul 04 04:48:23 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-ea4b0fdd-9b5c-4e1e-847b-3c9b1348e25c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108037821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.108037821 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.48921164 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4281772 ps |
| CPU time | 0.37 seconds |
| Started | Jul 04 04:48:22 PM PDT 24 |
| Finished | Jul 04 04:48:22 PM PDT 24 |
| Peak memory | 146016 kb |
| Host | smart-73ae7354-20aa-4124-8586-ac089499eb7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48921164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.48921164 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.945632186 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4631754 ps |
| CPU time | 0.36 seconds |
| Started | Jul 04 04:48:10 PM PDT 24 |
| Finished | Jul 04 04:48:11 PM PDT 24 |
| Peak memory | 146356 kb |
| Host | smart-60ecd7e2-bd87-43b7-9257-53283aa912e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945632186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.945632186 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3007357883 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4702599 ps |
| CPU time | 0.36 seconds |
| Started | Jul 04 04:48:15 PM PDT 24 |
| Finished | Jul 04 04:48:19 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-42b3fede-8f64-41bb-924d-82d506120946 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007357883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3007357883 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2668668113 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5202087 ps |
| CPU time | 0.39 seconds |
| Started | Jul 04 04:48:15 PM PDT 24 |
| Finished | Jul 04 04:48:21 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-e93c7722-0758-41bf-8c3e-969d027c5146 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668668113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2668668113 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2027534948 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4273143 ps |
| CPU time | 0.38 seconds |
| Started | Jul 04 04:48:23 PM PDT 24 |
| Finished | Jul 04 04:48:24 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-2646ddb9-b8f9-4713-bfa0-8daca41101a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027534948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2027534948 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.638392510 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4393476 ps |
| CPU time | 0.37 seconds |
| Started | Jul 04 04:48:19 PM PDT 24 |
| Finished | Jul 04 04:48:20 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-f4ae23e6-443b-4b2e-b1b1-f4e1c4f88cfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638392510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.638392510 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |