Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.53 85.53 92.38 92.38 82.93 82.93 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/9.prim_esc_test.3281724888
88.27 2.74 93.33 0.95 85.37 2.44 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/14.prim_esc_test.1417137257
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.1563532030
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/16.prim_esc_test.4008499156

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.223096196
/workspace/coverage/default/1.prim_esc_test.3984428183
/workspace/coverage/default/10.prim_esc_test.1628139198
/workspace/coverage/default/12.prim_esc_test.641825871
/workspace/coverage/default/13.prim_esc_test.67993680
/workspace/coverage/default/15.prim_esc_test.2436110049
/workspace/coverage/default/17.prim_esc_test.3441161645
/workspace/coverage/default/18.prim_esc_test.2211460777
/workspace/coverage/default/19.prim_esc_test.2502420345
/workspace/coverage/default/2.prim_esc_test.2340408349
/workspace/coverage/default/3.prim_esc_test.359494543
/workspace/coverage/default/4.prim_esc_test.2357778774
/workspace/coverage/default/5.prim_esc_test.2817298710
/workspace/coverage/default/6.prim_esc_test.3316588045
/workspace/coverage/default/7.prim_esc_test.2735682782
/workspace/coverage/default/8.prim_esc_test.3319549558



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_esc_test.3281724888 Jul 05 04:18:28 PM PDT 24 Jul 05 04:18:29 PM PDT 24 4560437 ps
T2 /workspace/coverage/default/5.prim_esc_test.2817298710 Jul 05 04:19:22 PM PDT 24 Jul 05 04:19:23 PM PDT 24 4822985 ps
T3 /workspace/coverage/default/15.prim_esc_test.2436110049 Jul 05 04:21:21 PM PDT 24 Jul 05 04:21:22 PM PDT 24 4457937 ps
T4 /workspace/coverage/default/14.prim_esc_test.1417137257 Jul 05 04:19:22 PM PDT 24 Jul 05 04:19:23 PM PDT 24 4697401 ps
T5 /workspace/coverage/default/16.prim_esc_test.4008499156 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 5186561 ps
T6 /workspace/coverage/default/12.prim_esc_test.641825871 Jul 05 04:23:01 PM PDT 24 Jul 05 04:23:01 PM PDT 24 4972421 ps
T13 /workspace/coverage/default/17.prim_esc_test.3441161645 Jul 05 04:22:57 PM PDT 24 Jul 05 04:22:58 PM PDT 24 4914516 ps
T11 /workspace/coverage/default/6.prim_esc_test.3316588045 Jul 05 04:18:36 PM PDT 24 Jul 05 04:18:37 PM PDT 24 4992131 ps
T14 /workspace/coverage/default/3.prim_esc_test.359494543 Jul 05 04:20:21 PM PDT 24 Jul 05 04:20:23 PM PDT 24 4290999 ps
T15 /workspace/coverage/default/1.prim_esc_test.3984428183 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 4634868 ps
T7 /workspace/coverage/default/13.prim_esc_test.67993680 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 4454195 ps
T16 /workspace/coverage/default/0.prim_esc_test.223096196 Jul 05 04:18:48 PM PDT 24 Jul 05 04:18:49 PM PDT 24 4919384 ps
T17 /workspace/coverage/default/19.prim_esc_test.2502420345 Jul 05 04:19:18 PM PDT 24 Jul 05 04:19:19 PM PDT 24 4689611 ps
T12 /workspace/coverage/default/18.prim_esc_test.2211460777 Jul 05 04:19:18 PM PDT 24 Jul 05 04:19:19 PM PDT 24 4866554 ps
T9 /workspace/coverage/default/10.prim_esc_test.1628139198 Jul 05 04:20:22 PM PDT 24 Jul 05 04:20:23 PM PDT 24 5243575 ps
T10 /workspace/coverage/default/2.prim_esc_test.2340408349 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 5132649 ps
T18 /workspace/coverage/default/7.prim_esc_test.2735682782 Jul 05 04:22:22 PM PDT 24 Jul 05 04:22:23 PM PDT 24 5019766 ps
T8 /workspace/coverage/default/8.prim_esc_test.3319549558 Jul 05 04:22:22 PM PDT 24 Jul 05 04:22:23 PM PDT 24 4765997 ps
T19 /workspace/coverage/default/4.prim_esc_test.2357778774 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 4957703 ps
T20 /workspace/coverage/default/11.prim_esc_test.1563532030 Jul 05 04:22:22 PM PDT 24 Jul 05 04:22:23 PM PDT 24 4601298 ps

Test location /workspace/coverage/default/9.prim_esc_test.3281724888
Short name T1
Test name
Test status
Simulation time 4560437 ps
CPU time 0.39 seconds
Started Jul 05 04:18:28 PM PDT 24
Finished Jul 05 04:18:29 PM PDT 24
Peak memory 146080 kb
Host smart-f2647fe9-4443-41a0-9ebc-c0f09105b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281724888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3281724888
Directory /workspace/9.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1417137257
Short name T4
Test name
Test status
Simulation time 4697401 ps
CPU time 0.41 seconds
Started Jul 05 04:19:22 PM PDT 24
Finished Jul 05 04:19:23 PM PDT 24
Peak memory 146072 kb
Host smart-58dd58ac-e0ba-475e-bd06-b3a04b6bd400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417137257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1417137257
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1563532030
Short name T20
Test name
Test status
Simulation time 4601298 ps
CPU time 0.41 seconds
Started Jul 05 04:22:22 PM PDT 24
Finished Jul 05 04:22:23 PM PDT 24
Peak memory 144800 kb
Host smart-4aa83371-3fe4-43ae-8494-f72543fd636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563532030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1563532030
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.4008499156
Short name T5
Test name
Test status
Simulation time 5186561 ps
CPU time 0.38 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145676 kb
Host smart-c8cd5d5f-0458-480a-a3d4-96eda653daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008499156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.4008499156
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.223096196
Short name T16
Test name
Test status
Simulation time 4919384 ps
CPU time 0.39 seconds
Started Jul 05 04:18:48 PM PDT 24
Finished Jul 05 04:18:49 PM PDT 24
Peak memory 146008 kb
Host smart-4b514605-e444-4c95-8bd6-cfece77e9705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223096196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.223096196
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3984428183
Short name T15
Test name
Test status
Simulation time 4634868 ps
CPU time 0.38 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145688 kb
Host smart-d53cc7ec-d675-4e5b-b72f-0a6c5f7c3091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984428183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3984428183
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1628139198
Short name T9
Test name
Test status
Simulation time 5243575 ps
CPU time 0.39 seconds
Started Jul 05 04:20:22 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 146000 kb
Host smart-7c27e59e-a20a-474c-b063-23c616c94bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628139198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1628139198
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.641825871
Short name T6
Test name
Test status
Simulation time 4972421 ps
CPU time 0.36 seconds
Started Jul 05 04:23:01 PM PDT 24
Finished Jul 05 04:23:01 PM PDT 24
Peak memory 145984 kb
Host smart-fb3075e9-65d5-4e12-9df6-d64f5517ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641825871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.641825871
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.67993680
Short name T7
Test name
Test status
Simulation time 4454195 ps
CPU time 0.37 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145740 kb
Host smart-a16ef74f-ed29-4290-a367-8ca5dca0ceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67993680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.67993680
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2436110049
Short name T3
Test name
Test status
Simulation time 4457937 ps
CPU time 0.39 seconds
Started Jul 05 04:21:21 PM PDT 24
Finished Jul 05 04:21:22 PM PDT 24
Peak memory 146008 kb
Host smart-7220a399-485f-486f-8fec-1e25d7b0e171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436110049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2436110049
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3441161645
Short name T13
Test name
Test status
Simulation time 4914516 ps
CPU time 0.38 seconds
Started Jul 05 04:22:57 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 145988 kb
Host smart-588946a4-7297-47be-bf17-16b96055b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441161645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3441161645
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2211460777
Short name T12
Test name
Test status
Simulation time 4866554 ps
CPU time 0.39 seconds
Started Jul 05 04:19:18 PM PDT 24
Finished Jul 05 04:19:19 PM PDT 24
Peak memory 146000 kb
Host smart-8eba46d7-92cd-4e82-8275-b279d9a550e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211460777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2211460777
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2502420345
Short name T17
Test name
Test status
Simulation time 4689611 ps
CPU time 0.4 seconds
Started Jul 05 04:19:18 PM PDT 24
Finished Jul 05 04:19:19 PM PDT 24
Peak memory 146000 kb
Host smart-d3083310-b30b-4cfb-97cc-a899ffe3293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502420345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2502420345
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2340408349
Short name T10
Test name
Test status
Simulation time 5132649 ps
CPU time 0.38 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145688 kb
Host smart-d0ac65d5-c488-4671-aefd-cef1076f9a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340408349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2340408349
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.359494543
Short name T14
Test name
Test status
Simulation time 4290999 ps
CPU time 0.39 seconds
Started Jul 05 04:20:21 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 146008 kb
Host smart-263a4d58-42b0-4459-a05e-21fd6098a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359494543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.359494543
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2357778774
Short name T19
Test name
Test status
Simulation time 4957703 ps
CPU time 0.37 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145740 kb
Host smart-c60c0f41-6532-4ca0-ae8d-403e1f28dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357778774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2357778774
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.2817298710
Short name T2
Test name
Test status
Simulation time 4822985 ps
CPU time 0.37 seconds
Started Jul 05 04:19:22 PM PDT 24
Finished Jul 05 04:19:23 PM PDT 24
Peak memory 146088 kb
Host smart-b43b7a5e-a620-4b53-bc8f-e77611e34fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817298710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2817298710
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.3316588045
Short name T11
Test name
Test status
Simulation time 4992131 ps
CPU time 0.37 seconds
Started Jul 05 04:18:36 PM PDT 24
Finished Jul 05 04:18:37 PM PDT 24
Peak memory 146008 kb
Host smart-c155f94e-8835-4d66-9779-1a5689337b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316588045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3316588045
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.2735682782
Short name T18
Test name
Test status
Simulation time 5019766 ps
CPU time 0.42 seconds
Started Jul 05 04:22:22 PM PDT 24
Finished Jul 05 04:22:23 PM PDT 24
Peak memory 144776 kb
Host smart-14719dbf-91a7-4713-84d7-d4b24cf0e12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735682782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2735682782
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3319549558
Short name T8
Test name
Test status
Simulation time 4765997 ps
CPU time 0.39 seconds
Started Jul 05 04:22:22 PM PDT 24
Finished Jul 05 04:22:23 PM PDT 24
Peak memory 144680 kb
Host smart-c429c98a-81aa-4d52-9f63-c2c731dbcde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319549558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3319549558
Directory /workspace/8.prim_esc_test/latest
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